EPM7160STC100-6N vs EPM7160EQC100-20 비교

다음의 상세 나란히 비교: EPM7160STC100-6N 제조: Altera 및 EPM7160EQC100-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Altera
EPM7160EQC100-20 EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 ⚠ 최종 구매

사양 비교

파라미터 EPM7160STC100-6N EPM7160EQC100-20
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete 최종 구매
재고 상태 In Stock In Stock
단가 (USD) $14.20 $17.10
Family MAX 7000S MAX 7000 CPLD
Logic Type CPLD (Complex Programmable Logic Device) —
Macro Cells 160 —
User I/Os 84 —
Gates (typical) 3,200 —
Propagation Delay (tPD) 6 ns —
Internal Frequency 149.3 MHz (max) —
공급 전압 5 V —
Program Memory Type EEPROM (non-volatile) —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (IEEE 1149.1 JTAG, 4-pin)
패키지 TQFP-100 (T100) 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100)
Package Code LFQFP, S Gull-Wing —
동작 온도 0 °C to +70 °C (Commercial) 0 °C to +90 °C (commercial)
Logic Family CMOS —
I/O Banks [DATA_NEEDED: I/O bank count] —
RoHS 상태 [DATA_NEEDED: RoHS compliance] Not RoHS compliant (legacy Altera MAX 7000)
Lead-Free [DATA_NEEDED: lead-free status] —
Series — MAX 7000
Architecture — CMOS EEPROM-based, non-volatile
Usable Gates — 3,200
Macrocells — 160
Logic Array Blocks (LABs) — 10
Maximum User I/Os — 84
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Maximum Internal Frequency (fCNT) — 62.5 MHz
Supply Voltage (VCCINT) — 5 V nominal (4.75 V to 5.25 V)
I/O Voltage Support — 3.3 V or 5 V configurable
실장 유형 — Surface Mount
Reprogram Cycles (typical) — 100
Logic Elements per Macrocell — 36 product terms (expandable)

데이터시트 & 자료

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