EPM7192EGC160-12 vs EPM7192EQC160-20 对比

详细并排对比 EPM7192EGC160-12 出自 Intel 和 EPM7192EQC160-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7192EGC160-12 EPM7192EQC160-20
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $10.85 $58.26
Series MAX 7000 MAX 7000
Device Family MAX 7000E (EPM7192E) —
Macrocells 192 —
Logic Array Blocks (LABs) 4 —
Usable Gates 3.75K —
User I/O Pins 124 —
Propagation Delay (tPD) 12 ns —
Maximum Operating Frequency 76.9 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) 4.75 V to 5.25 V
Process Technology CMOS, EEPROM-based —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
封装 160-BPGA / PGA-160 (39.6 x 39.6 mm) —
安装类型 Through-Hole (Pin Grid Array, socketable) Surface Mount
工作温度 0 C to +90 C (Commercial) -40C to +85C (industrial)
RoHS 状态 [DATA_NEEDED: RoHS status - not stated in provided web data] [DATA_NEEDED: RoHS status - non-RoHS era part]
Programmable Type — EE PLD (EEPROM-based)
Number of Macrocells — 192
Number of Logic Array Blocks — 4
Number of User I/O Pins — 124 (per package), 36 (per data source variant description)
Delay Time (tPD) — 20 ns
Internal Counter Frequency (fCNT) — 100 MHz typical
封装 / 外壳 — 160-BQFP / 160-PQFP (28x28 mm)
In-System Programmable (ISP) — Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1)
Programmable Security Bit — Yes
Power-Saving Mode — Yes, programmable per macrocell
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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