EPM7256AETC100-10N vs EPM7256AEFI100-7 对比

详细并排对比 EPM7256AETC100-10N 出自 Altera 和 EPM7256AEFI100-7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256AETC100-10N EPM7256AEFI100-7
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $13.10 $65.40
Family MAX 7000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 —
Usable Gates 5,000 —
Maximum User I/Os 84 —
Logic Elements / LABs 16 Logic Array Blocks —
Pin-to-Pin Logic Delay 10 ns —
Maximum Operating Frequency 125 MHz 126.6 MHz
Supply Voltage (Core) 3.3 V —
MultiVolt I/O Support 2.5 V / 3.3 V / 5.0 V 2.5 V / 3.3 V / 5.0 V
Programmability EEPROM, in-system via JTAG (IEEE 1149.1) In-system programmable (ISP) via JTAG
封装 100-pin TQFP 100-ball FBGA (FineLine BGA), 11x11 mm
安装类型 Surface Mount Surface Mount
工作温度范围 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] —
Process Technology 0.30 µm EEPROM —
Dedicated Inputs 4 (global clock / clear / OE) —
RoHS 状态 [DATA_NEEDED: not confirmed in provided data] Not Compliant (per Arrow listing)
Lead-Free / Pb-Free [DATA_NEEDED: not confirmed in provided data] —
Logic Family — MAX 7000A
Number of Macrocells — 256
Number of Usable Gates — 5K
Number of User I/O — 84
Pin-to-Pin Delay (Speed Grade) — 7.5 ns
Core Supply Voltage — 3.3 V
Operating Temperature Range (Industrial) — -40 C to +85 C
JTAG / Boundary Scan — IEEE 1149.1 compliant

数据手册与资源

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