EPM7256SQC208-15 vs EPM7256SQI208-10 对比

详细并排对比 EPM7256SQC208-15 出自 Altera 和 EPM7256SQI208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256SQC208-15 EPM7256SQI208-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3.65 $0.40
Family MAX 7000S —
Series EPM7256 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 256 256
Logic Array Blocks (LABs) 16 —
Usable Gates 5000 5000
User I/O Pins 164 —
Pin-to-Pin Delay (tPD) 15 ns —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
工作温度范围 0 C to +70 C (Commercial) -40 C to +85 C (Industrial)
封装 208-pin PQFP (28x28 mm) 208-pin PQFP (QFP208)
安装类型 Surface Mount Surface Mount
Programmable Power Mode Yes (per-macrocell turbo-bit) —
JTAG (IEEE 1149.1) Boundary-Scan Yes —
In-System Programmability (ISP) Yes —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
RoHS 状态 Contains lead / RoHS non-compliant (per third-party listing) [DATA_NEEDED: RoHS status]
Lead-Free Status Contains lead —
Device Family — MAX 7000 (EPM7256)
Logic Array Blocks — 16
Maximum User I/O Pins — 164
Propagation Delay (tPD) — 10 ns
Supply Voltage Range — 4.5 V to 5.5 V
Technology — CMOS EEPROM
In-System Programmable — Yes (IEEE 1149.1 JTAG)
Package Body Material — Plastic/Epoxy
Terminal Form — Gull Wing
JESD-30 Package Code — S-PQFP-G208
JESD-609 Terminal Finish Code — E3

数据手册与资源

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