EPM7256SQC208-15N vs EPM7256SQC208-15 对比

详细并排对比 EPM7256SQC208-15N 出自 Altera 和 EPM7256SQC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256SQC208-15N EPM7256SQC208-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $3.65
Series MAX 7000S EPM7256
Macrocells 256 256
User I/O Pins 164 164
Pin-to-Pin Delay 15 ns (speed grade -15) —
电源电压 5 V —
封装 208-pin PQFP 208-pin PQFP (28x28 mm)
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
JTAG Interface IEEE 1149.1 boundary-scan —
In-System Programmability Yes (ISP) —
工作温度 [DATA_NEEDED: operating temperature range] —
RoHS 状态 Lead free / RoHS Compliant Contains lead / RoHS non-compliant (per third-party listing)
Logic Array Blocks 16 macrocells per LAB —
Interconnect Programmable Interconnect Array (PIA) —
Speed Grade -15 —
Product Category CPLD - Complex Programmable Logic Devices —
Manufacturer Altera (Intel Programmable Solutions Group) —
Family — MAX 7000S
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
Usable Gates — 5000
Pin-to-Pin Delay (tPD) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
工作温度范围 — 0 C to +70 C (Commercial)
Programmable Power Mode — Yes (per-macrocell turbo-bit)
JTAG (IEEE 1149.1) Boundary-Scan — Yes
In-System Programmability (ISP) — Yes
Lead-Free Status — Contains lead

数据手册与资源

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