EPM7256SQC208-7N vs EPM7256SQC208-15N 对比
详细并排对比 EPM7256SQC208-7N 出自 Altera 和 EPM7256SQC208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256SQC208-7N | EPM7256SQC208-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.20 | $0.00 |
| Family | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | 164 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | -15 |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | EEPROM (non-volatile) |
| 封装 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | IEEE 1149.1 boundary-scan |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| RoHS 状态 | Compliant (N suffix = lead-free) | Lead free / RoHS Compliant |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Open-Drain Output | Optional per I/O pin | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| 电源电压 | — | 5 V |
| In-System Programmability | — | Yes (ISP) |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |