EPM7256SRC208-10 vs EPM7256SQC208-15 对比

详细并排对比 EPM7256SRC208-10 出自 Intel 和 EPM7256SQC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256SRC208-10 EPM7256SQC208-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $27.20 $3.65
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Number of Macrocells 256 —
Number of Logic Array Blocks (LABs) 16 —
Number of Gates 5000 —
Number of User I/O Pins 164 —
Maximum Propagation Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (Internal) 4.75 V to 5.25 V —
Programmable Type In System Programmable (ISP, JTAG) —
Configuration Technology EEPROM —
封装 208-pin RQFP (BFQFP) exposed pad, 28x28 mm 208-pin PQFP (28x28 mm)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (TA, commercial) —
Terminal Form Gull Wing —
Package Shape Square —
Product Status Obsolete —
RoHS 状态 [DATA_NEEDED: RoHS status] Contains lead / RoHS non-compliant (per third-party listing)
Series — EPM7256
Macrocells — 256
Logic Array Blocks (LABs) — 16
Usable Gates — 5000
User I/O Pins — 164
Pin-to-Pin Delay (tPD) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
工作温度范围 — 0 C to +70 C (Commercial)
Programmable Power Mode — Yes (per-macrocell turbo-bit)
JTAG (IEEE 1149.1) Boundary-Scan — Yes
In-System Programmability (ISP) — Yes
Configuration Memory — EEPROM (non-volatile)
Lead-Free Status — Contains lead

数据手册与资源

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