EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel
料号： EPM9320LC84-15 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $17.95 | $17,950.00 |
EPM9320LC84-15 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on characteristics of classic PAL/GAL architectures with the density of modern FPGAs. The MAX architecture organizes logic into Logic Array Blocks (LABs) interconnected by a programmable interconnect matrix, with each macrocell containing a product-term array, a programmable flip-flop, and configurable I/O steering - placing CPLDs in the hierarchy: macrocell -> LAB -> CPLD -> programmable logic -> semiconductor device.
The EPM9320LC84-15 supports a maximum clock frequency of 117.6 MHz and provides up to 212 user I/O pins in the largest package of the family. Its pin-locking architecture ensures that any change to the user's logic design does not alter pin assignments, simplifying PCB layout and design migration. The device also supports JTAG-based IEEE 1149.1 boundary-scan testing and includes built-in pull-up resistors on every I/O for reliable tri-state bus interfacing.
Typical applications include bus interface bridging (PCI-to-ISA, address decoding), peripheral glue logic, state-machine controllers, and high-performance control logic replacement for multiple SSI/MSI components. Designers commonly deploy the EPM9320LC84-15 in telecom backplane controllers, industrial automation I/O expanders, and legacy system upgrades where 5 V tolerant logic and deterministic 15 ns timing are required.
When designing with this device, ensure VCC ramps monotonically between 4.75 V and 5.25 V per the operating requirements; undershoot below -0.5 V or overshoot above 7.0 V on I/O pins (under no-load conditions, for periods shorter than 20 ns) is permissible only during fast transitions. Decoupling with 0.1 microfarad and 10 microfarad capacitors adjacent to every VCC pin is recommended.
直接替换替代料： EPM9320LC84-15 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9320LC84-15 （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Supply Voltage (VCC), Usable Gates, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
EPM9320LC84-10
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$84.96 / 个
查看数据手册 →EPM9320LC84-20
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EPM9320ALC84-15
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.95 / 个
查看数据手册 →EPM9320ALC84-20
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$10.5 / 个
查看数据手册 →EPM9320ALI84-10
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$19.95 / 个
查看数据手册 →EPM9320GC280-15
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$92.5 / 个
查看数据手册 →EPM9320LC84-15 最大额定值与电气特性
| Family | MAX 9000 |
| Series | EPM9320 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 |
| Logic Array Blocks (LABs) | 20 |
| Propagation Delay (tPD) | 15 ns (max) |
| 最大时钟频率 | 117.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant |
| 封装 | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| 安装类型 | Surface Mount |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | Yes, on every I/O pin |
| Architecture Feature | Pin-locking across design iterations |
EPM9320LC84-15 引脚配置
| 引脚 1 | I/O — User I/O pin (bank 1) |
| 引脚 2 | I/O — User I/O pin (bank 1) |
| 引脚 3 | I/O — User I/O pin (bank 1) |
| 引脚 4 | I/O — User I/O pin (bank 1) |
| 引脚 5 | I/O — User I/O pin (bank 1) |
| 引脚 6 | I/O — User I/O pin (bank 1) |
| 引脚 7 | I/O — User I/O pin (bank 1) |
| 引脚 8 | I/O — User I/O pin (bank 1) |
| 引脚 9 | I/O — User I/O pin (bank 1) |
| 引脚 10 | I/O — User I/O pin (bank 1) |
| 引脚 11 | I/O — User I/O pin (bank 1) |
| 引脚 12 | GND — Ground |
| 引脚 13 | I/O — User I/O pin (bank 2) |
| 引脚 14 | I/O — User I/O pin (bank 2) |
| 引脚 15 | I/O — User I/O pin (bank 2) |
| 引脚 16 | I/O — User I/O pin (bank 2) |
| 引脚 17 | I/O — User I/O pin (bank 2) |
| 引脚 18 | I/O — User I/O pin (bank 2) |
| 引脚 19 | I/O — User I/O pin (bank 2) |
| 引脚 20 | I/O — User I/O pin (bank 2) |
| 引脚 21 | I/O — User I/O pin (bank 2) |
| 引脚 22 | I/O — User I/O pin (bank 2) |
| 引脚 23 | I/O — User I/O pin (bank 2) |
| 引脚 24 | I/O — User I/O pin (bank 2) |
| 引脚 25 | GND — Ground |
| 引脚 26 | I/O — User I/O pin (bank 3) |
| 引脚 27 | I/O — User I/O pin (bank 3) |
| 引脚 28 | I/O — User I/O pin (bank 3) |
| 引脚 29 | I/O — User I/O pin (bank 3) |
| 引脚 30 | I/O — User I/O pin (bank 3) |
| 引脚 31 | I/O — User I/O pin (bank 3) |
| 引脚 32 | I/O — User I/O pin (bank 3) |
| 引脚 33 | I/O — User I/O pin (bank 3) |
| 引脚 34 | I/O — User I/O pin (bank 3) |
| 引脚 35 | I/O — User I/O pin (bank 3) |
| 引脚 36 | I/O — User I/O pin (bank 3) |
| 引脚 37 | GND — Ground |
| 引脚 38 | I/O — User I/O pin (bank 4) |
| 引脚 39 | I/O — User I/O pin (bank 4) |
| 引脚 40 | I/O — User I/O pin (bank 4) |
| 引脚 41 | I/O — User I/O pin (bank 4) |
| 引脚 42 | I/O — User I/O pin (bank 4) |
| 引脚 43 | I/O — User I/O pin (bank 4) |
| 引脚 44 | I/O — User I/O pin (bank 4) |
| 引脚 45 | I/O — User I/O pin (bank 4) |
| 引脚 46 | I/O — User I/O pin (bank 4) |
| 引脚 47 | I/O — User I/O pin (bank 4) |
| 引脚 48 | I/O — User I/O pin (bank 4) |
| 引脚 49 | GND — Ground |
| 引脚 50 | I/O — User I/O pin (bank 5) |
| 引脚 51 | I/O — User I/O pin (bank 5) |
| 引脚 52 | I/O — User I/O pin (bank 5) |
| 引脚 53 | I/O — User I/O pin (bank 5) |
| 引脚 54 | I/O — User I/O pin (bank 5) |
| 引脚 55 | I/O — User I/O pin (bank 5) |
| 引脚 56 | I/O — User I/O pin (bank 5) |
| 引脚 57 | I/O — User I/O pin (bank 5) |
| 引脚 58 | I/O — User I/O pin (bank 5) |
| 引脚 59 | I/O — User I/O pin (bank 5) |
| 引脚 60 | I/O — User I/O pin (bank 5) |
| 引脚 61 | GND — Ground |
| 引脚 62 | I/O — User I/O pin (bank 6) |
| 引脚 63 | I/O — User I/O pin (bank 6) |
| 引脚 64 | I/O — User I/O pin (bank 6) |
| 引脚 65 | I/O — User I/O pin (bank 6) |
| 引脚 66 | I/O — User I/O pin (bank 6) |
| 引脚 67 | I/O — User I/O pin (bank 6) |
| 引脚 68 | I/O — User I/O pin (bank 6) |
| 引脚 69 | I/O — User I/O pin (bank 6) |
| 引脚 70 | I/O — User I/O pin (bank 6) |
| 引脚 71 | I/O — User I/O pin (bank 6) |
| 引脚 72 | I/O — User I/O pin (bank 6) |
| 引脚 73 | GND — Ground |
| 引脚 74 | TDI — JTAG Test Data In |
| 引脚 75 | TMS — JTAG Test Mode Select |
| 引脚 76 | TCK — JTAG Test Clock |
| 引脚 77 | TDO — JTAG Test Data Out |
| 引脚 78 | VCC — 5.0 V supply |
| 引脚 79 | DEV_CLRn — Device-wide clear (active-low) |
| 引脚 80 | DEV_OE — Device-wide output enable (active-low) |
| 引脚 81 | INPUT/GCLK — Dedicated input / Global clock |
| 引脚 82 | INPUT — Dedicated input pin |
| 引脚 83 | INPUT — Dedicated input pin |
| 引脚 84 | INPUT — Dedicated input pin |
典型应用
EPM9320LC84-15 适用于 6 应用s: PCI-to-ISA Bus Bridge Controller, Glue Logic Integration for Industrial Controllers, State Machine Controller for Telecom Backplanes, Legacy Peripheral Decoder and Address Mapper, Test and Measurement Front-End Logic, Aerospace and Military Avionics Interface Logic.
PCI-to-ISA Bus Bridge Controller
The EPM9320LC84-15's 320 macrocells and 117.6 MHz clock capability make it ideal for implementing legacy PCI-to-ISA bus bridges. Its 15 ns propagation delay comfortably meets the ISA bus timing specification of 8 MHz operation with ample margin for address decoding, command translation, and interrupt arbitration. With 6,000 usable gates and 84 user I/O pins, designers can integrate the address decoder, wait-state generator, and DMA arbiter into a single device. Pin-locking across design iterations simplifies PCB layout when late-stage logic changes occur.
推荐
Glue Logic Integration for Industrial Controllers
Industrial automation systems often require custom glue logic between microprocessors, memory, and peripherals - exactly the niche where the EPM9320LC84-15 excels. The device's 320 macrocells can absorb dozens of 74-series TTL chips, replacing hundreds of SSI/MSI gates with a single 5 V tolerant CPLD. Its 5 V in-system programmability via JTAG allows field upgrades without removing the controller from the line, while 15 ns timing provides deterministic interrupt latency and bus-cycle control. The 84-pin PLCC supports sufficient I/O for typical PLC backplane designs.
推荐
State Machine Controller for Telecom Backplanes
Telecom backplane controllers require reliable, deterministic state machines for protocol handling, line-card arbitration, and alarm generation. The EPM9320LC84-15's pin-locking MAX 9000 architecture ensures that design revisions do not shift pins, preserving backplane routing while logic evolves. With 117.6 MHz maximum frequency and 15 ns propagation delay, the device handles T1/E1 framing, HDLC bit stuffing, and HDB3 encoding comfortably. JTAG boundary-scan support simplifies in-system test and field diagnostics across the backplane.
推荐
Legacy Peripheral Decoder and Address Mapper
Embedded systems with x86, 68k, or PowerPC processors often need custom peripheral decoders and address-mapped register blocks. The EPM9320LC84-15's 6,000 gates handle the equivalent of 10-15 standard PAL devices in a single chip, reducing board area and improving noise immunity. Its 15 ns delay satisfies the address-to-chip-select timing required by ISA, PC/104, and VMEbus peripherals. The JTAG ISP capability enables late-stage BOM changes and field firmware updates without rework.
推荐
Test and Measurement Front-End Logic
Test instruments require precise timing, deterministic sequencing, and reconfigurable control logic - all areas where the EPM9320LC84-15 provides strong value. Its 15 ns propagation delay and 117.6 MHz fMAX support sub-50 ns trigger-to-response paths in oscilloscope front-ends, logic analyzers, and arbitrary waveform generators. The 320-macrocell capacity can integrate pattern generators, sequencers, and parallel data formatters in a single device, while the 5 V supply noise margin suits the analog front-end mixed-signal environments typical of measurement equipment.
推荐
Aerospace and Military Avionics Interface Logic
The EPM9320LC84-15 serves in legacy avionics and military systems where 5 V tolerance, deterministic timing, and radiation-tolerant MAX architecture are critical. Its 15 ns tPD and JTAG boundary-scan compliance meet the testability requirements of DO-254 and MIL-STD-883 designs. The pin-locking feature protects against post-radiation logic remap shifts, and the EEPROM-based configuration provides non-volatile instant-on behavior essential for safety-critical flight systems. Designers should verify MIL-spec variants explicitly with the manufacturer for flight-qualified deployments.
推荐
推荐产品汇总
工程参考数据： EPM9320LC84-15 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320ALC84-15 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) |
| Macrocells | 320 | 320 | 320 | 320 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster) | 20 ns (slower) | 15 ns (same) |
| Maximum Clock Frequency | 117.6 MHz | ~147 MHz (faster) | ~100 MHz (slower) | 117.6 MHz (same) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes |
关键差异点
- Balanced speed grade for legacy 5 V systems （对比 EPM9320LC84-20)
- Cost-effective speed upgrade path （对比 EPM9320LC84-10)
- Pin-locking across design revisions （对比 Generic non-pin-locked CPLDs)
设计说明
Decouple every VCC pin (78 and additional bank VCCs on the 84-PLCC) with a 0.1 microfarad ceramic capacitor placed within 5 mm of the pin. Add a bulk 10 microfarad tantalum or ceramic capacitor on each side of the package. Per the Altera MAX 9000 datasheet, VCC must rise monotonically between 4.75 V and 5.25 V; any negative-going slope or dip below 4.75 V can corrupt the EEPROM configuration cells and require re-programming via JTAG.
Route TCK, TMS, TDI, and TDO (pins 74-77) with short, matched-length traces and a 4.7 kilohm pull-up on TCK/TMS/TDI per IEEE 1149.1 convention. Maintain at least 2 mm spacing between JTAG traces and clock or switching signals to prevent boundary-scan corruption. Keep the JTAG connector near the device to minimize stub length.
Per the Altera MAX 9000 datasheet, undershoot below -0.5 V or overshoot above 7.0 V on I/O pins is permissible only under no-load conditions for periods shorter than 20 ns. Add 22 ohm series resistors at outputs driving long traces to dampen ringing. Use the built-in pull-up resistors on every I/O to hold unused pins in a defined state.
Estimated: When migrating designs from EPM9320LC84-15 to EPM9320LC84-10, ensure the faster 10 ns propagation delay does not introduce hold-time violations in synchronous paths. Conversely, when downgrading to EPM9320LC84-20, verify that critical timing paths (typically address decoding and strobe generation) still meet setup requirements at the lower fMAX.
合规信息
MAX 9000 family predates modern RoHS documentation in available web data; the original Altera datasheet (46 pages, 569 KB) does not explicitly state RoHS compliance. Verify RoHS status with the manufacturer before designing into RoHS-restricted products. AEC-Q100 is not applicable for commercial/industrial CPLDs.