EPM9320ALC84-20 vs EPM9320LC84-15 对比
详细并排对比 EPM9320ALC84-20 出自 Altera 和 EPM9320LC84-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320ALC84-20 | EPM9320LC84-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.50 | $17.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| 封装 | PLCC-84 | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| 电源电压 | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | 5.0 V in-system programmable (ISP) via JTAG |
| 工作温度 | [DATA_NEEDED: commercial or industrial grade] | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| 安装类型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS 状态 | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Usable Gates | — | 6,000 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| 最大时钟频率 | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |