EPM9320ALC84-20 vs EPM9320LC84-20 对比
详细并排对比 EPM9320ALC84-20 出自 Altera 和 EPM9320LC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320ALC84-20 | EPM9320LC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.50 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| 封装 | PLCC-84 | PLCC-84 (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| 电源电压 | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| 工作温度 | [DATA_NEEDED: commercial or industrial grade] | 0 C to 70 C |
| 安装类型 | Surface Mount (PLCC socket compatible) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS 状态 | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Counter Frequency | — | 118 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |