EPM9320ALC84-20 vs EPM9320LC84-20 Comparison
Detailed side-by-side comparison of EPM9320ALC84-20 by Altera and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-20 | EPM9320LC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Package | PLCC-84 | PLCC-84 (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | 0 C to 70 C |
| Mounting Type | Surface Mount (PLCC socket compatible) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS Status | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Counter Frequency | — | 118 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |