EPM9320ALI84-10N vs EPM9320ALC84-15 对比
详细并排对比 EPM9320ALI84-10N 出自 Altera 和 EPM9320ALC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320ALI84-10N | EPM9320ALC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.95 | $9.95 |
| Family | MAX 9000 | MAX 9000 CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | — |
| Usable Gates | 6,000 to 12,000 | 6000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| 封装 | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC (S-PQCC-J84, J-lead) |
| 安装类型 | Surface Mount (PLCC socket compatible) | Through-hole / socket |
| 工作温度 | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Configuration Memory | EEPROM, non-volatile | — |
| Propagation Delay (tPD) | — | 16 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| User I/O | — | 56 |
| Technology | — | CMOS, EEPROM-based configuration |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| RoHS 状态 | — | [DATA_NEEDED: rohs status] |
| 湿敏等级（MSL） | — | MSL-3 (168 hours per fpgalink.com) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead free status] |
| RoHS3 Compliance | — | ROHS3 Compliant (per fpgalink.com listing) |