EPM9320ALI84-10N vs EPM9320ALC84-20 对比
详细并排对比 EPM9320ALI84-10N 出自 Altera 和 EPM9320ALC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320ALI84-10N | EPM9320ALC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.95 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | 0.5 µm CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| 封装 | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 |
| 安装类型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| 工作温度 | -40C to +85C (industrial) | [DATA_NEEDED: commercial or industrial grade] |
| Configuration Memory | EEPROM, non-volatile | Non-volatile EEPROM |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| 电源电压 | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |
| RoHS 状态 | — | [DATA_NEEDED: per Altera datasheet] |