EPM9320ALI84-10N vs EPM9320ALC84-20 比較
詳細な並列比較: EPM9320ALI84-10N メーカー: Altera および EPM9320ALC84-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320ALI84-10N | EPM9320ALC84-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.95 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | 0.5 µm CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| パッケージ | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| 動作温度 | -40C to +85C (industrial) | [DATA_NEEDED: commercial or industrial grade] |
| Configuration Memory | EEPROM, non-volatile | Non-volatile EEPROM |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| 電源電圧 | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |
| RoHS ステータス | — | [DATA_NEEDED: per Altera datasheet] |