EPM9320ARC208-10N vs EPM9320RI208-10N 对比

详细并排对比 EPM9320ARC208-10N 出自 Altera 和 EPM9320RI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ 量产中

规格对比

参数 EPM9320ARC208-10N EPM9320RI208-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $19.45 $27.20
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) Complex Programmable Logic Device (CPLD)
Macro Cells 320 320
Logic Gates 6,000 gates —
Logic Array Blocks (LABs) 16 20
Propagation Delay (tPD) 10 ns —
Maximum Frequency 144.9 MHz —
Supply Voltage (VCC) 5 V —
User I/O Pins 168 160
Dedicated Input Pins 12 —
封装 208-pin RQFP (BFQFP with exposed pad) 208-pin RQFP (PowerQuad II)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (Commercial) —
Programming Interface IEEE Std. 1149.1 JTAG —
Configuration Memory Non-volatile EEPROM EEPROM (non-volatile)
RoHS 状态 Compliant (lead-free 'N' suffix) Compliant (N suffix = lead-free)
Usable Gates — 6,000
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum System Clock Frequency — 100 MHz
电源电压 — 5 V
I/O Voltage — 5 V
In-System Programmability — Yes (JTAG/ISP)
工作温度范围 — -40C to +85C (industrial)
Lead Finish — Lead-free (matte tin)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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