EPM9320LI84-20N vs EPM9320LC84-10 对比
详细并排对比 EPM9320LI84-20N 出自 Altera 和 EPM9320LC84-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320LI84-20N | EPM9320LC84-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $84.96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6000 (typical) |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| 封装 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (JEDEC MO-047) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | — |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| 电源电压 | 5.0 V | — |
| 工作温度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | 0.7 µm CMOS EEPROM/UV-EPROM |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | ROHS3 Compliant (per fpgalink listing) |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | — | 5.0 V (typical, see datasheet) |
| 安装类型 | — | Surface Mount (PLCC socket also common) |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| 湿敏等级（MSL） | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |