EPM9320LI84-20N vs EPM9320LC84-10 비교
다음의 상세 나란히 비교: EPM9320LI84-20N 제조: Altera 및 EPM9320LC84-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9320LI84-20N | EPM9320LC84-10 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $84.96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6000 (typical) |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| 패키지 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (JEDEC MO-047) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | — |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| 공급 전압 | 5.0 V | — |
| 동작 온도 | 0 C to +70 C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | 0.7 µm CMOS EEPROM/UV-EPROM |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | ROHS3 Compliant (per fpgalink listing) |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | — | 5.0 V (typical, see datasheet) |
| 실장 유형 | — | Surface Mount (PLCC socket also common) |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| 습도 민감도 레벨 (MSL) | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |