EPM9320RC208-15N vs EPM9320RI208-20N 对比

详细并排对比 EPM9320RC208-15N 出自 Intel 和 EPM9320RI208-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320RC208-15N EPM9320RI208-20N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $0.00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 —
Macro Cells 320 —
Flip-Flops 484 484
Configurable I/O Lines 128 —
Propagation Delay (tPD) 15 ns 20 ns
最大时钟频率 117.6 MHz —
电源电压 5.0 V —
I/O Voltage Compatibility 3.3 V or 5 V —
Configuration Technology CMOS EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes, 5.0 V ISP via JTAG
封装 208-pin RQFP (PowerQuad Flat Pack) 208-pin PQFP (Plastic Quad Flat Pack)
Terminal Pitch 0.5 mm —
工作温度范围 0C to +70C (commercial) -40C to +85C (Industrial)
安装类型 Surface Mount Surface Mount
Packaging Tray —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000 (EPM9320)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells — 320
Supply Voltage (VCC) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5 V configurable
Package Lead Pitch — 0.500 mm
Number of Terminals — 208
JTAG Interface — IEEE Std. 1149.1 compliant
Configuration Memory — EEPROM (non-volatile)
Dedicated Input Pins — 4 (low-skew global distribution)
Minimum DC Input on I/O Pins — -0.5 V
Minimum DC Input on Dedicated Inputs — -0.3 V
Input Undershoot/ Overshoot — -2.0 V / 7.0 V for <20 ns (no-load)

数据手册与资源

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