EPM9480RC208-15N vs EPM9560RI208-15N 对比

详细并排对比 EPM9480RC208-15N 出自 Altera 和 EPM9560RI208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9480RC208-15N EPM9560RI208-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $19.45
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Usable Gates 10,000 —
Macro Cells 480 —
Maximum Frequency 117.6 MHz —
Propagation Delay 15 ns (speed grade -15) —
电源电压 5.0 V 5.0 V
封装 208-pin RQFP 208-pin RQFP (Ruggedized Quad Flat Pack)
安装类型 Surface Mount —
Configuration Memory EEPROM (non-volatile) CMOS EEPROM, in-system programmable
In-System Programmability Yes (ISP via JTAG) —
JTAG Interface IEEE Std. 1149.1 —
工作温度 [DATA_NEEDED: operating temperature range] 0C to 70C (Commercial)
RoHS 状态 ROHS3 Compliant [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level MSL 3 (168 Hours) —
Manufacturer Standard Lead Time 1-7 Days —
Architecture Multiple Array MatriX (MAX) third-generation Multiple Array MatriX (MAX), 3rd generation
Manufacturer — Altera (Intel Programmable Solutions Group)
Device Family — MAX 9000
Total Pins — 356 (per third-party catalog; see _validation_note)
Package Pin Count — 208
Terminal Form — Gull Wing
Package Code — HFQFP
User I/Os — 216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency — 145 MHz
Propagation Delay (tPD) — 11.4 ns (15 ns speed grade)
Speed Grade — -15
Temperature Grade — Industrial (per Vyrian/Partstack listings)
Logic Family — CMOS
Programming Interface — IEEE 1149.1 JTAG, 5.0-V in-system

数据手册与资源

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