EPM9480RC208-15N vs EPM9560RI208-15N Comparison

Detailed side-by-side comparison of EPM9480RC208-15N by Altera and EPM9560RI208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9480RC208-15N EPM9560RI208-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Usable Gates 10,000 —
Macro Cells 480 —
Maximum Frequency 117.6 MHz —
Propagation Delay 15 ns (speed grade -15) —
Supply Voltage 5.0 V 5.0 V
Package 208-pin RQFP 208-pin RQFP (Ruggedized Quad Flat Pack)
Mounting Type Surface Mount —
Configuration Memory EEPROM (non-volatile) CMOS EEPROM, in-system programmable
In-System Programmability Yes (ISP via JTAG) —
JTAG Interface IEEE Std. 1149.1 —
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to 70C (Commercial)
RoHS Status ROHS3 Compliant [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level MSL 3 (168 Hours) —
Manufacturer Standard Lead Time 1-7 Days —
Architecture Multiple Array MatriX (MAX) third-generation Multiple Array MatriX (MAX), 3rd generation
Manufacturer — Altera (Intel Programmable Solutions Group)
Device Family — MAX 9000
Total Pins — 356 (per third-party catalog; see _validation_note)
Package Pin Count — 208
Terminal Form — Gull Wing
Package Code — HFQFP
User I/Os — 216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency — 145 MHz
Propagation Delay (tPD) — 11.4 ns (15 ns speed grade)
Speed Grade — -15
Temperature Grade — Industrial (per Vyrian/Partstack listings)
Logic Family — CMOS
Programming Interface — IEEE 1149.1 JTAG, 5.0-V in-system

Datasheets & Resources

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