EPM9560ARC240-10 vs EPM9560R1208-20 对比

详细并排对比 EPM9560ARC240-10 出自 Altera 和 EPM9560R1208-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC240-10 EPM9560R1208-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $28.80 $22.40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Usable Gates 12,000 6,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz —
Propagation Delay (tpd) 11.4 ns —
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
封装 240-pin PowerQuad QFP (RQFP / EAR240) R-1208 (BGA-style fine-pitch)
工作温度 0C to +70C (commercial) 0C to +70C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) On-chip EEPROM (non-volatile)
Logic Family CMOS —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks — 52 (typical for 560 macrocells)
Maximum User I/O — 212
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
安装类型 — Surface Mount
Boundary-Scan Test — JTAG IEEE Std. 1149.1

数据手册与资源

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