EPM9560ARC240-10 vs EPM9560R1208-20 Comparison

Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC240-10 EPM9560R1208-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $28.80 $22.40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Usable Gates 12,000 6,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) β€”
Internal Frequency 144.9 MHz β€”
Propagation Delay (tpd) 11.4 ns β€”
Supply Voltage - Internal (VCCINT) 5.0 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) β€”
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Package 240-pin PowerQuad QFP (RQFP / EAR240) R-1208 (BGA-style fine-pitch)
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) On-chip EEPROM (non-volatile)
Logic Family CMOS β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks β€” 52 (typical for 560 macrocells)
Maximum User I/O β€” 212
Propagation Delay (tPD) β€” 20 ns
Maximum Frequency (fMAX) β€” 125 MHz
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Mounting Type β€” Surface Mount
Boundary-Scan Test β€” JTAG IEEE Std. 1149.1

Datasheets & Resources

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