EPM9560ARI240-10N vs EPM9560ARI240-10 对比

详细并排对比 EPM9560ARI240-10N 出自 Intel 和 EPM9560ARI240-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARI240-10N EPM9560ARI240-10
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $0.00
Family MAX 9000 MAX 9000
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 12,000
Macrocells 560 —
Logic Array Blocks (LABs) 16 —
User I/Os 216 (per digchip); 191 (per Mouser) —
Maximum Internal Frequency 144.9 MHz (typical); 145 MHz (per digchip) —
Propagation Delay (tPD) 10 ns (-10 speed grade) —
电源电压 5.0 V nominal (4.5 V min, 5.5 V max) 5.0 V
Logic Family CMOS, EEPROM-based —
In-System Programmability Yes (5.0 V ISP via JTAG) —
封装 240-pin RQFP (RQFP-240 / PQFP-240) 240-pin RQFP (PowerQuad Flat Pack)
安装类型 Surface Mount Surface Mount
工作温度 -40C to +85C (industrial) —
Architecture Multiple Array MatriX (MAX) - 3rd generation —
JTAG (IEEE 1149.1) Yes —
Lead-Free / RoHS [DATA_NEEDED: lead-free / RoHS status not in provided data] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 560
User I/O Pins — 191
Pin-to-Pin Propagation Delay — 10 ns
Internal Frequency — 144.9 MHz
Technology — CMOS, EEPROM-based configuration
工作温度范围 — -40 C to +85 C (industrial)
Configuration Memory — EEPROM (non-volatile, instant-on)
Logic Architecture — Multiple Array MatriX (MAX) with global interconnect array
RoHS 状态 — [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level — [DATA_NEEDED: MSL level]
Number of Terminals — 240
Terminal Form — Gull Wing

数据手册与资源

浏览全部产品 创建 BOM 获取报价