EPM9560ELI84-20 vs EPM9400LC84-20 对比

详细并排对比 EPM9560ELI84-20 出自 Altera 和 EPM9400LC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ELI84-20 EPM9400LC84-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $19.50 $38.50
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX) - EEPROM-based Multiple Array Matrix (MAX), 3rd generation, EEPROM-based
Usable Gates 6,000 8,000 (6,000 to 12,000 typical range)
Macrocells 560 400
Logic Array Blocks (LABs) 16 —
Maximum User I/O 212 (package-dependent) 55
Flip-Flops 212 580
Pin-to-Pin Propagation Delay 20 ns 20 ns (speed grade -20)
Speed Grade -20 —
Supply Voltage (VCC) 5.0 V —
In-System Programmability 5.0 V ISP via IEEE 1149.1 JTAG —
I/O Standards 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) —
封装 84-pin PLCC 84-pin PLCC (Plastic Leaded Chip Carrier)
安装类型 Through-Hole / Socket Surface Mount (PLCC socket or SMT land pattern)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Process Technology CMOS EEPROM CMOS EEPROM
工作温度 -40C to +85C (industrial) Commercial (0C to +70C) - assumed from -20 speed grade
Device Type — CPLD (Complex Programmable Logic Device)
Maximum Counter Frequency — 144 MHz
Supply Voltage (VCCINT) — 5 V
I/O Voltage (VCCIO) — 3.3 V or 5 V (configurable)
In-System Programming — Yes (IEEE 1149.1 JTAG)

数据手册与资源

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