EPM9560GI280-20 vs EPM9560R1208-20 对比
详细并排对比 EPM9560GI280-20 出自 Intel 和 EPM9560R1208-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560GI280-20 | EPM9560R1208-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $162.50 | $22.40 |
| Device Family | MAX 9000 | — |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Technology Node | 5.0 V CMOS EEPROM | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | — |
| Usable Gates | 12,000 | 6,000 |
| Maximum User I/O Pins | 216 | — |
| Flip-Flops | 772 | — |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | EEPROM (non-volatile) | — |
| 封装 | 280-pin PGA (PIN/PEG, square) | R-1208 (BGA-style fine-pitch) |
| Terminal Form | PIN/PEG (through-hole PGA) | — |
| Package Code | PGA | — |
| Temperature Grade | Industrial | — |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | — |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | — |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | — |
| VCC Ramp Requirement | Monotonic rise | — |
| Development Tool | Altera MAX+PLUS II | — |
| Supported HDLs | VHDL, Verilog HDL, AHDL | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status for GI PGA package] | [DATA_NEEDED: confirm via current distributor data] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | — | 52 (typical for 560 macrocells) |
| Maximum User I/O | — | 212 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| 工作温度 | — | 0C to +70C (commercial) |
| 安装类型 | — | Surface Mount |
| Process Technology | — | CMOS EEPROM, third-generation MAX architecture |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |