EPM9560RC208-10 vs EPM9560RC208-12 对比

详细并排对比 EPM9560RC208-10 出自 Intel 和 EPM9560RC208-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC208-10 EPM9560RC208-12
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $15.40 $0.00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EEPROM-based CPLD
Macrocells 560 560
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 (208-pin package variant) —
Usable Gates 12,000 12000
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] —
Supply Voltage (VCCINT) 5.0 V 5 V
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) —
Configuration Memory EEPROM (in-system programmable via JTAG) EEPROM (non-volatile)
Process Technology 0.30 µm CMOS EEPROM —
工作温度 0C to +70C (commercial) 0C to +70C (commercial)
封装 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (S-PQFP-G208)
安装类型 Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] —
RoHS 状态 [DATA_NEEDED: not stated in retrieved distributor listings] [DATA_NEEDED: RoHS status]
Programmability JTAG (IEEE 1149.1) in-system programming —
Flip-Flops — 772
User I/O Lines — 153
Propagation Delay (tPD) — 12 ns
最大时钟频率 — 125 MHz
I/O Voltage Compatibility — 3.3 V or 5 V
Terminal Pitch — 0.50 mm
Logic Array Blocks — 20
Speed Grade — -12 (12 ns)

数据手册与资源

浏览全部产品 创建 BOM 获取报价