EPM9560RC208-10 vs EPM9560RC208-12 Comparison

Detailed side-by-side comparison of EPM9560RC208-10 by Intel and EPM9560RC208-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-10 EPM9560RC208-12
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.40 $0.00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EEPROM-based CPLD
Macrocells 560 560
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 212 (208-pin package variant) β€”
Usable Gates 12,000 12000
Pin-to-Pin Delay (tPD) 10 ns β€”
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] β€”
Supply Voltage (VCCINT) 5.0 V 5 V
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) β€”
Configuration Memory EEPROM (in-system programmable via JTAG) EEPROM (non-volatile)
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Package 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (S-PQFP-G208)
Mounting Type Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] β€”
RoHS Status [DATA_NEEDED: not stated in retrieved distributor listings] [DATA_NEEDED: RoHS status]
Programmability JTAG (IEEE 1149.1) in-system programming β€”
Flip-Flops β€” 772
User I/O Lines β€” 153
Propagation Delay (tPD) β€” 12 ns
Maximum Clock Frequency β€” 125 MHz
I/O Voltage Compatibility β€” 3.3 V or 5 V
Terminal Pitch β€” 0.50 mm
Logic Array Blocks β€” 20
Speed Grade β€” -12 (12 ns)

Datasheets & Resources

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