EPM9560RC208-13 vs EPM9560RC208-18 对比

详细并排对比 EPM9560RC208-13 出自 Altera 和 EPM9560RC208-18 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC208-13 EPM9560RC208-18
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 停产
库存状态 有库存 有库存
单价(USD) $0.00 $0.00
Device Family MAX 9000 EPLD MAX 9000 (EPM9560)
Macrocells 560 560 macrocells
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 20 —
User I/O Pins 208 —
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Package Code RC208 —
Speed Grade -13 (13 ns pin-to-pin) —
Propagation Delay (tPD) 13 ns 18 ns (speed grade -18)
最大时钟频率 125 MHz —
电源电压 5.0 V 5 V
Configuration Technology EEPROM (non-volatile) —
Programming Interface IEEE 1149.1 JTAG —
工作温度范围 0C to +70C (commercial) —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free Status [DATA_NEEDED: lead-free status] —
MSL 等级 [DATA_NEEDED: MSL level] —
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Maximum Operating Frequency — 117.6 MHz (family -15 grade reference)
I/O Voltage Compatibility — 3.3 V or 5 V
User I/O Lines — 149 I/O lines
Flip-Flops — 772 flip-flops
Package JESD-30 Code — S-PQFP-G208
Configuration Memory — EEPROM (non-volatile, no external config PROM)
Technology — CMOS
工作温度 — [DATA_NEEDED: operating temperature range]
生命周期状态 — EOL / mature (per Altera product discontinuance notice)

数据手册与资源

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