EPM9560RC208-15N vs EPM9480RC208-15N 对比

详细并排对比 EPM9560RC208-15N 出自 Intel 和 EPM9480RC208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM9560RC208-15N EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N ⚠ 最后一次采购

规格对比

参数 EPM9560RC208-15N EPM9480RC208-15N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $19.85 $0.00
Series MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 560 —
Usable Gates 12,000 10,000
Logic Array Blocks (LABs) 16 —
User I/O 212 (in 208-RQFP, see family datasheet) —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Internal Frequency 117.6 MHz —
Supply Voltage (VCCINT) 5.0 V —
Programmability In-system via IEEE 1149.1 JTAG —
Configuration Memory CMOS EEPROM (non-volatile) EEPROM (non-volatile)
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP
Operating Temperature (commercial) 0C to +70C —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: check part marking suffix for lead-free/RoHS] ROHS3 Compliant
Speed Grade -15 (15 ns tPD) —
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) third-generation
Family — MAX 9000
Macro Cells — 480
Maximum Frequency — 117.6 MHz
Propagation Delay — 15 ns (speed grade -15)
电源电压 — 5.0 V
In-System Programmability — Yes (ISP via JTAG)
JTAG Interface — IEEE Std. 1149.1
工作温度 — [DATA_NEEDED: operating temperature range]
Moisture Sensitivity Level — MSL 3 (168 Hours)
Manufacturer Standard Lead Time — 1-7 Days

数据手册与资源

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