EPM9560RC208-18 vs EPM9560RC208-19 对比

详细并排对比 EPM9560RC208-18 出自 Altera 和 EPM9560RC208-19 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC208-18 EPM9560RC208-19
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 停产 Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $16.20
Device Family MAX 9000 (EPM9560) MAX 9000
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 gates 12,000
Macrocells 560 macrocells 560
Propagation Delay (tPD) 18 ns (speed grade -18) 19 ns
Maximum Operating Frequency 117.6 MHz (family -15 grade reference) —
电源电压 5 V —
I/O Voltage Compatibility 3.3 V or 5 V —
User I/O Lines 149 I/O lines —
Flip-Flops 772 flip-flops 772
封装 208-pin RQFP (Power Quad Flat Pack) RQFP-208 (208-pin PQFP)
Package JESD-30 Code S-PQFP-G208 —
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile, no external config PROM) —
Technology CMOS CMOS EEPROM
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
生命周期状态 EOL / mature (per Altera product discontinuance notice) —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — [DATA_NEEDED: LAB count]
User I/O Pins — 149
Maximum Frequency — [DATA_NEEDED: fMAX]
Supply Voltage (VCCINT) — 5.0 V
I/O Voltage Tolerance — 3.3 V / 5 V
In-System Programmability — Yes (IEEE 1149.1 JTAG)
JEDEC Package Code — S-PQFP-G208

数据手册与资源

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