EPM9560RC208-18 vs EPM9560RC208-19 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-19 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-19 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | End of Life | Obsolete |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macrocells | 560 macrocells | 560 |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | 19 ns |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Supply Voltage | 5 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| User I/O Lines | 149 I/O lines | — |
| Flip-Flops | 772 flip-flops | 772 |
| Package | 208-pin RQFP (Power Quad Flat Pack) | RQFP-208 (208-pin PQFP) |
| Package JESD-30 Code | S-PQFP-G208 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | — |
| Technology | CMOS | CMOS EEPROM |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| User I/O Pins | — | 149 |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| JEDEC Package Code | — | S-PQFP-G208 |