EPM9560RC208-7 vs EPM9560RC208-20 对比

详细并排对比 EPM9560RC208-7 出自 Altera 和 EPM9560RC208-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC208-7 EPM9560RC208-20
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $18.90 $0.00
Family MAX 9000 —
Device Type EPLD / CPLD —
Usable Gates 560 12,000
Macrocells 16 560
Logic Array Blocks (LABs) 4 —
User I/O Pins 208 153
Pin-to-Pin Delay (tPD) 7 ns (speed grade -7) 20 ns
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Supply Voltage (VCCINT) 5.0 V —
Supply Voltage (VCCIO) 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) —
Process Technology 0.65 um CMOS EEPROM —
Configuration Memory Non-volatile on-chip EEPROM (no boot PROM required) —
Programming Interface JTAG (IEEE 1149.1) + Altera ISP —
封装 208-pin Power Quad Flat Pack (RQFP-208) 208-pin RQFP (28x28 mm)
工作温度 0C to +70C (commercial) / -40C to +85C (industrial) 0C to +70C (commercial)
Output Drive Current 160 mA DC sink per pin —
RoHS 状态 Compliant (ROHS3 per distributor listing) [DATA_NEEDED: RoHS status]
Device Family — MAX 9000 (EPM9560)
Logic Array Blocks — 35
最大时钟频率 — 100 MHz
电源电压 — 5.0 V
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
安装类型 — Surface Mount
I/O Standards — 5.0 V TTL/CMOS compatible
Flip-Flops — 772
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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