EPM9560RC210-20 vs EPM9560RI210-15 对比

详细并排对比 EPM9560RC210-20 出自 Altera 和 EPM9560RI210-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ 最后一次采购

规格对比

参数 EPM9560RC210-20 EPM9560RI210-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 不推荐新设计
库存状态 有库存 有库存
单价(USD) $60.00 $0.00
Family MAX 9000 MAX 9000 (EPM9560)
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 20
封装 RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) 210-pin RQFP (PowerQuad)
Pin-to-Pin Delay (tPD) 20 ns 15 ns (-15 speed grade)
Clock-to-Output (tCO) 12 ns —
Maximum User I/O [DATA_NEEDED: 212 I/O per datasheet, package-dependent] —
电源电压 5 V —
Process Technology 0.65 um EEPROM —
In-System Programmability Yes (MAX+PLUS II flow) Yes (JTAG ISP)
Boundary-Scan (JTAG) IEEE Std 1149.1 compliant —
工作温度 [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] Industrial (-40C to +85C)
安装类型 Surface Mount Surface Mount
RoHS 状态 RoHS3 Compliant (per supplier listing) ROHS3 Compliant
Device Type — Complex Programmable Logic Device (CPLD)
User I/O Pins — 164
Supply Voltage (VCCINT) — 5.0 V
I/O Voltage (MultiVolt) — 3.3 V / 5.0 V compatible
Configuration Memory — EEPROM (non-volatile)
JTAG Boundary Scan — IEEE 1149.1 compliant
湿敏等级(MSL) — 3 (168 Hours)
Manufacturer Standard Lead Time — 1-7 Days (distributor stock)

数据手册与资源

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