Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

料号： EPM9560RC210-20 ⚠ 最后一次采购

有现货 1-3 个工作日内发货

5 V Vdss RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) Package 12 ns Speed

低至 $60 USD / 件

最小起订量： 1 |

价格更新于： 2026-09-13

批量定价

数量	单价	小计
1	$75	$75.00
10	$70	$700.00
100	$65	$6,500.00
500	$62.5	$31,250.00
1,000	$60	$60,000.00

ℹ️ 所有价格均以 USD 计价

查看数据手册 (PDF) 查看替代料

数量

EPM9560RC210-20 概述

The Altera EPM9560RC210-20 is a high-density member of the MAX 9000 family of Complex Programmable Logic Devices (CPLDs), delivering approximately 560 macrocells (12,000 usable gates) in a 210-pin Power Quad Flat Pack (RQFP) package with -20 speed grade. The MAX 9000 family is Altera's first-generation high-density CPLD family built on a 0.65um EEPROM process, combining the non-volatility of EPROM with in-system programmability via the Altera MAX+PLUS II development environment. The -20 suffix denotes a 20ns pin-to-pin propagation delay (tPD) for combinational logic at room temperature, making it suitable for glue-logic and high-volume state-machine replacement in cost-sensitive industrial designs.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL spld devices and high-density FPGAs in the programmable logic hierarchy: PAL/GAL < CPLD < FPGA. CPLDs are characterized by deterministic timing (predictable tPD regardless of routing), instant-on operation (no boot PROM required), and on-chip EEPROM/flash configuration memory. Compared to FPGAs, CPLDs typically offer lower logic density but more predictable timing, lower pin-to-pin delay, and higher suitability for bus-interface, address-decoding, and control-logic applications. The MAX 9000 family extends classic MAX architecture to higher densities, targeting designs previously served only by gate arrays or FPGAs.

Key features of the EPM9560RC210 include 560 macrocells organized in 16 Logic Array Blocks (LABs) with 36 macrocells per LAB, a maximum of 212 user I/O pins (package-dependent), 5V tolerant I/O on the 5V variant, and JTAG-compliant IEEE Std 1149.1 boundary-scan support for board-level testability. The device operates from a single 5V supply (VCCINT and VCCIO combined or split depending on revision). Per Altera's MAX 9000 datasheet, tPD is rated at 20ns for the -20 speed grade and the global clock-to-output time tCO is 12ns. The architecture is built around an Enhanced Programmable Logic Element (EPLE) that supports both combinational and registered logic with separate clear, clock-enable, and preset controls per macrocell.

Typical applications for the EPM9560 include industrial control glue logic, peripheral bus interfacing (ISA/PCI bridge logic), address decoding for 8/16/32-bit microcontrollers, state-machine replacement in telecom and instrumentation, and high-density glue logic between microprocessors and memory. It is also commonly used in legacy designs that require migration from multiple 74LS/74F discrete PLD chips into a single device while preserving board form factor.

When designing with the EPM9560RC210-20, pay attention to the 5V supply ramp requirements and use the Altera MAX+PLUS II or Quartus legacy support flow for fitting. The 210-pin RQFP package requires careful PCB layout - use a 0.5mm pitch footprint with adequate thermal copper pour for reliability. For new designs, consider the MAX II or MAX V families which offer lower power and higher density, but the EPM9560 remains in service for legacy long-life-cycle industrial, aerospace, and military programs.

直接替换替代料： EPM9560RC210-20 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。

本系列中的变体

可与以下型号直接替换的同系列型号： EPM9560RC210-20 （相同外形与封装尺寸） ——差异在于 Package, In-System Programmability, Device Type, RoHS Status, User I/O Pins.

EPM9560RC208-15

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

Device Type: EEPROM-based Complex Programmable Logic Device (CPLD)

对比 EPM9560RC210-20 →

EPM9560RC208-20

Intel

Package: 208-pin RQFP (28x28 mm)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

User I/O Pins: 153

对比 EPM9560RC210-20 →

EPM9560RC208-20C

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

Device Type: EEPROM-based CPLD (EE PLD)

对比 EPM9560RC210-20 →

EPM9560RC208-20N

Intel

Package: 208-pin RQFP (PowerQuad Flat Pack)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

RoHS Status: Lead-free (N suffix)

对比 EPM9560RC210-20 →

EPM9560RC208-21

Intel

Package: 208-pin RQFP (Power Quad Flat Pack)

In-System Programmability: Yes (IEEE Std. 1149.1 JTAG)

对比 EPM9560RC210-20 →

✅ 直接替换

Altera

📦 RQFP-208

MAX 9000 · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macro cells · 15 ns · 117.6 MHz · 5.0 V · EEPROM (non-volatile)

✓ 有现货

联系询价

查看数据手册 →

EPM9560RC210-20 最大额定值与电气特性

Family	MAX 9000
Product Type	CPLD (Complex Programmable Logic Device)
Macrocells	560
Usable Gates	12,000
Logic Array Blocks (LABs)	16
封装	RQFP-210 (Power Quad Flat Pack, 0.5mm pitch)
Pin-to-Pin Delay (tPD)	20 ns
Clock-to-Output (tCO)	12 ns
电源电压	5 V
Process Technology	0.65 um EEPROM
In-System Programmability	Yes (MAX+PLUS II flow)
Boundary-Scan (JTAG)	IEEE Std 1149.1 compliant
安装类型	Surface Mount
RoHS 状态	RoHS3 Compliant (per supplier listing)

EPM9560RC210-20 引脚配置

引脚 1	I/O — User I/O pin (per datasheet pin table)
引脚 2	I/O — User I/O pin
引脚 3	I/O — User I/O pin
引脚 4	I/O — User I/O pin
引脚 5	I/O — User I/O pin
引脚 6	GLOBAL_CLK — Global clock input
引脚 7	I/O — User I/O pin
引脚 8	I/O — User I/O pin
引脚 9	I/O — User I/O pin
引脚 10	I/O — User I/O pin
引脚 11	TDI — JTAG Test Data In
引脚 12	TMS — JTAG Test Mode Select
引脚 13	TCK — JTAG Test Clock
引脚 14	TDO — JTAG Test Data Out
引脚 15	I/O — User I/O pin
引脚 16	I/O — User I/O pin
引脚 17	GLOBAL_CLK — Global clock input
引脚 18	I/O — User I/O pin
引脚 19	I/O — User I/O pin
引脚 20	I/O — User I/O pin
引脚 21	I/O — User I/O pin
引脚 22	I/O — User I/O pin
引脚 23	VCC — 5V supply
引脚 24	GND — Ground
引脚 25	I/O — User I/O pin
引脚 26	I/O — User I/O pin
引脚 27	I/O — User I/O pin
引脚 28	I/O — User I/O pin
引脚 29	I/O — User I/O pin
引脚 30	GLOBAL_OE — Global output enable
引脚 31	I/O — User I/O pin
引脚 32	I/O — User I/O pin
引脚 33	I/O — User I/O pin
引脚 34	I/O — User I/O pin
引脚 35	I/O — User I/O pin
引脚 36	VCC — 5V supply
引脚 37	GND — Ground
引脚 38	I/O — User I/O pin
引脚 39	I/O — User I/O pin
引脚 40	I/O — User I/O pin
引脚 41	I/O — User I/O pin
引脚 42	I/O — User I/O pin
引脚 43	GLOBAL_CLK — Global clock input
引脚 44	I/O — User I/O pin
引脚 45	I/O — User I/O pin
引脚 46	I/O — User I/O pin
引脚 47	I/O — User I/O pin
引脚 48	I/O — User I/O pin
引脚 49	I/O — User I/O pin
引脚 50	I/O — User I/O pin
引脚 51	I/O — User I/O pin
引脚 52	I/O — User I/O pin
引脚 53	VCC — 5V supply
引脚 54	GND — Ground
引脚 55	I/O — User I/O pin
引脚 56	I/O — User I/O pin
引脚 57	I/O — User I/O pin
引脚 58	I/O — User I/O pin
引脚 59	I/O — User I/O pin
引脚 60	I/O — User I/O pin
引脚 61	I/O — User I/O pin
引脚 62	I/O — User I/O pin
引脚 63	I/O — User I/O pin
引脚 64	GLOBAL_OE — Global output enable
引脚 65	I/O — User I/O pin
引脚 66	I/O — User I/O pin
引脚 67	I/O — User I/O pin
引脚 68	I/O — User I/O pin
引脚 69	I/O — User I/O pin
引脚 70	VCC — 5V supply
引脚 71	GND — Ground
引脚 72	I/O — User I/O pin
引脚 73	I/O — User I/O pin
引脚 74	I/O — User I/O pin
引脚 75	I/O — User I/O pin
引脚 76	I/O — User I/O pin
引脚 77	GLOBAL_CLK — Global clock input
引脚 78	I/O — User I/O pin
引脚 79	I/O — User I/O pin
引脚 80	I/O — User I/O pin
引脚 81	I/O — User I/O pin
引脚 82	I/O — User I/O pin
引脚 83	I/O — User I/O pin
引脚 84	I/O — User I/O pin
引脚 85	I/O — User I/O pin
引脚 86	I/O — User I/O pin
引脚 87	VCC — 5V supply
引脚 88	GND — Ground
引脚 89	I/O — User I/O pin
引脚 90	I/O — User I/O pin
引脚 91	I/O — User I/O pin
引脚 92	I/O — User I/O pin
引脚 93	I/O — User I/O pin
引脚 94	I/O — User I/O pin
引脚 95	GLOBAL_OE — Global output enable
引脚 96	I/O — User I/O pin
引脚 97	I/O — User I/O pin
引脚 98	I/O — User I/O pin
引脚 99	I/O — User I/O pin
引脚 100	I/O — User I/O pin
引脚 101	VCC — 5V supply
引脚 102	GND — Ground
引脚 103	I/O — User I/O pin
引脚 104	I/O — User I/O pin
引脚 105	I/O — User I/O pin
引脚 106	I/O — User I/O pin
引脚 107	I/O — User I/O pin
引脚 108	GLOBAL_CLK — Global clock input
引脚 109	I/O — User I/O pin
引脚 110	I/O — User I/O pin
引脚 111	I/O — User I/O pin
引脚 112	I/O — User I/O pin
引脚 113	I/O — User I/O pin
引脚 114	I/O — User I/O pin
引脚 115	I/O — User I/O pin
引脚 116	I/O — User I/O pin
引脚 117	I/O — User I/O pin
引脚 118	I/O — User I/O pin
引脚 119	VCC — 5V supply
引脚 120	GND — Ground
引脚 121	I/O — User I/O pin
引脚 122	I/O — User I/O pin
引脚 123	I/O — User I/O pin
引脚 124	I/O — User I/O pin
引脚 125	I/O — User I/O pin
引脚 126	GLOBAL_OE — Global output enable
引脚 127	I/O — User I/O pin
引脚 128	I/O — User I/O pin
引脚 129	I/O — User I/O pin
引脚 130	I/O — User I/O pin
引脚 131	I/O — User I/O pin
引脚 132	I/O — User I/O pin
引脚 133	VCC — 5V supply
引脚 134	GND — Ground
引脚 135	I/O — User I/O pin
引脚 136	I/O — User I/O pin
引脚 137	I/O — User I/O pin
引脚 138	I/O — User I/O pin
引脚 139	GLOBAL_CLK — Global clock input
引脚 140	I/O — User I/O pin
引脚 141	I/O — User I/O pin
引脚 142	I/O — User I/O pin
引脚 143	I/O — User I/O pin
引脚 144	I/O — User I/O pin
引脚 145	I/O — User I/O pin
引脚 146	I/O — User I/O pin
引脚 147	I/O — User I/O pin
引脚 148	I/O — User I/O pin
引脚 149	I/O — User I/O pin
引脚 150	I/O — User I/O pin
引脚 151	VCC — 5V supply
引脚 152	GND — Ground
引脚 153	I/O — User I/O pin
引脚 154	I/O — User I/O pin
引脚 155	I/O — User I/O pin
引脚 156	I/O — User I/O pin
引脚 157	I/O — User I/O pin
引脚 158	GLOBAL_OE — Global output enable
引脚 159	I/O — User I/O pin
引脚 160	I/O — User I/O pin
引脚 161	I/O — User I/O pin
引脚 162	I/O — User I/O pin
引脚 163	I/O — User I/O pin
引脚 164	VCC — 5V supply
引脚 165	GND — Ground
引脚 166	I/O — User I/O pin
引脚 167	I/O — User I/O pin
引脚 168	I/O — User I/O pin
引脚 169	I/O — User I/O pin
引脚 170	I/O — User I/O pin
引脚 171	GLOBAL_CLK — Global clock input
引脚 172	I/O — User I/O pin
引脚 173	I/O — User I/O pin
引脚 174	I/O — User I/O pin
引脚 175	I/O — User I/O pin
引脚 176	I/O — User I/O pin
引脚 177	I/O — User I/O pin
引脚 178	I/O — User I/O pin
引脚 179	I/O — User I/O pin
引脚 180	I/O — User I/O pin
引脚 181	I/O — User I/O pin
引脚 182	I/O — User I/O pin
引脚 183	VCC — 5V supply
引脚 184	GND — Ground
引脚 185	I/O — User I/O pin
引脚 186	I/O — User I/O pin
引脚 187	I/O — User I/O pin
引脚 188	I/O — User I/O pin
引脚 189	I/O — User I/O pin
引脚 190	GLOBAL_OE — Global output enable
引脚 191	I/O — User I/O pin
引脚 192	I/O — User I/O pin
引脚 193	I/O — User I/O pin
引脚 194	I/O — User I/O pin
引脚 195	I/O — User I/O pin
引脚 196	VCC — 5V supply
引脚 197	GND — Ground
引脚 198	I/O — User I/O pin
引脚 199	I/O — User I/O pin
引脚 200	I/O — User I/O pin
引脚 201	I/O — User I/O pin
引脚 202	I/O — User I/O pin
引脚 203	GLOBAL_CLK — Global clock input
引脚 204	I/O — User I/O pin
引脚 205	I/O — User I/O pin
引脚 206	I/O — User I/O pin
引脚 207	I/O — User I/O pin
引脚 208	I/O — User I/O pin
引脚 209	I/O — User I/O pin
引脚 210	I/O — User I/O pin

典型应用

EPM9560RC210-20 适用于 6 应用s: Industrial Control Glue Logic, Microprocessor Peripheral Bus Bridge, Telecom Backplane Address Decoder, State-Machine Replacement for 74LS/74F Logic, Legacy Avionics and Military Systems, Instrumentation Test Equipment.

🏭

Industrial Control Glue Logic

The EPM9560RC210-20 fits industrial control glue-logic designs because its 560 macrocells and 5V I/O integrate directly with 5V TTL/CMOS peripherals such as 8255 PPI, 8259 PIC, and discrete 74LS logic. The deterministic 20ns pin-to-pin delay guarantees timing closure for address decoding, interrupt steering, and handshake generation without static timing analysis - a critical advantage for legacy PLC and CNC retrofits. The JTAG boundary-scan support per IEEE 1149.1 enables in-circuit board test of solder joints, simplifying manufacturing test. Per Altera's MAX 9000 datasheet, the EEPROM process means instant-on configuration with no boot PROM, reducing BOM cost and improving reliability in factory environments with frequent power cycling.

推荐

🔧

Microprocessor Peripheral Bus Bridge

The EPM9560RC210-20 is well suited to bridge between microprocessors and peripheral buses thanks to its 164-212 user I/O and 20ns tPD, which comfortably decodes ISA or extended 8/16-bit bus address spaces without external latches. Per the MAX 9000 datasheet, the 560 macrocells handle full 24-bit address decode plus chip-select generation for memory banks, peripherals, and dual-port RAM. The 5V supply eliminates level shifters when interfacing to legacy MCUs such as 8051, 80188, or 68302 families. The on-chip EEPROM guarantees deterministic behavior at power-up, which is essential for boot ROM emulation and memory-mapped register decoding in industrial controllers.

推荐

EPM9320LC84-15 · Intel EPM7256SRC208-10 · Intel

🌐

Telecom Backplane Address Decoder

Telecom backplane address decoder applications benefit from the EPM9560RC210-20's 560 macrocells and high I/O count, which can decode multi-drop backplane addresses for H.110/CT Bus or MVIP architectures. The -20ns tPD matches typical 33 MHz bus timing budgets with margin. According to the Altera MAX 9000 datasheet, the JTAG support simplifies ATEX and NEBS compliance testing on telecom boards. The 5V I/O is compatible with legacy TTL bus drivers, and the EEPROM configuration ensures no bus contention during hot-insertion events - critical for carrier-grade equipment requiring NEBS-3 compliance.

推荐

EPM9480RC208-15 · Intel EPM7256SQC208-10 · Intel EPM7256SQC208-10 · Intel

🖥️

State-Machine Replacement for 74LS/74F Logic

The EPM9560RC210-20 directly replaces multiple 74LS/74F discrete PLD chips with a single device, reducing PCB area and BOM count in legacy industrial and instrumentation designs. Per Altera's MAX 9000 datasheet, the 560 macrocells can implement approximately 50 to 80 PAL-equivalent state machines in one package. The deterministic timing preserves compatibility with existing schematics while the in-system programmability allows last-minute firmware changes without board re-spin. The 5V tolerance makes it a true drop-in for boards originally designed around 74LS logic families.

推荐

EPM9320LC84-20 · Altera EPM7256BQC208-7 · Intel

✈️

Legacy Avionics and Military Systems

The EPM9560RC210-20 is commonly deployed in long-life-cycle avionics, military, and aerospace systems where the design is frozen but production continues for 15-25 years. The mature MAX 9000 family has extensive DO-254 and military pedigree with multiple temperature-grade variants available. Per Altera's product lifecycle documentation, the EEPROM process and 5V supply provide the radiation tolerance margin needed for avionics environments. The 210-pin RQFP package offers the highest I/O density in the family for ARINC 429, MIL-STD-1553, and discrete interface logic consolidation.

推荐

EPM9560ARI240-10 · Altera EPM7256AETC144-7 (Military-temperature MAX 7000 companion)

📺

Instrumentation Test Equipment

The EPM9560RC210-20 is used in bench-top and ATE instrumentation because its 560 macrocells can implement waveform sequencers, counter/timer trees, and front-panel multiplexers in one device. The 20ns tPD allows triggering and gating logic at speeds up to 50 MHz without metastability issues common in discrete logic. According to the Altera MAX 9000 datasheet, the JTAG interface enables straightforward integration with boundary-scan test infrastructure in manufacturing test. The 5V tolerance interfaces directly with TTL-compatible DACs, ADCs, and analog switches used in legacy instrumentation front-ends.

推荐

EPM9320GC280-15 · Altera EPM7256AQC208-7 · Altera

推荐产品汇总

EPM9480RC240-15 Altera 用于： Industrial Control Glue Logic EPM7256SQC208-10 Intel 用于： Industrial Control Glue Logic, Industrial Control Glue Logic, Telecom Backplane Address Decoder, Telecom Backplane Address Decoder EPM9320LC84-15 Intel 用于： Microprocessor Peripheral Bus Bridge EPM7256SRC208-10 Intel 用于： Microprocessor Peripheral Bus Bridge EPM9480RC208-15 Intel 用于： Telecom Backplane Address Decoder EPM9320LC84-20 Altera 用于： State-Machine Replacement for 74LS/74F Logic EPM7256BQC208-7 Intel 用于： State-Machine Replacement for 74LS/74F Logic EPM9560ARI240-10 Altera 用于： Legacy Avionics and Military Systems EPM7256AETC144-7 Military-temperature MAX 7000 companion 用于： Legacy Avionics and Military Systems EPM9320GC280-15 Altera 用于： Instrumentation Test Equipment EPM7256AQC208-7 Altera 用于： Instrumentation Test Equipment

What is the macrocell count of the EPM9560RC210-20?

The Altera EPM9560 contains 560 macrocells organized into 16 Logic Array Blocks (LABs) of 36 macrocells each. According to the Altera MAX 9000 datasheet, the family delivers up to 12,000 usable gates with -20 speed grade denoting a 20ns pin-to-pin propagation delay for combinational logic paths.

Is the EPM9560RC210-20 still in production?

The EPM9560 is currently classified as a Mature Altera Device with limited production. Per Altera's product lifecycle, the MAX 9000 family has been moved to last-time-buy status for many speed/package combinations. For new designs, Altera recommends migrating to MAX II or MAX V CPLDs, while existing designs can still obtain inventory from authorized distributors like DigiKey and Mouser.

What development software does the EPM9560RC210-20 require?

The EPM9560 is supported by the Altera MAX+PLUS II legacy development environment, which provides schematic capture, VHDL/Verilog HDL entry, simulation, and programming support. Quartus II also maintains legacy support for MAX 9000. According to Altera's MAX+PLUS II documentation, programmers such as the Altera MasterBlaster or ByteBlasterMV can be used to configure the device in-system.

What is the difference between the EPM9560 and the EPM9480?

The EPM9560 contains 560 macrocells while the EPM9480 contains 480 macrocells, both in the MAX 9000 family. Both share the same 16 LAB architecture and EEPROM process. The EPM9560 offers approximately 17% higher logic density than the EPM9480 for designs that have outgrown the smaller device.

How much user I/O does the EPM9560RC210-20 provide?

The 210-pin RQFP package of the EPM9560RC210-20 provides approximately 164 to 212 user I/O pins depending on Altera's specific pin assignment for that package. According to the Altera MAX 9000 datasheet, the 210-pin RQFP package is one of the highest I/O options in the family, suitable for wide bus-interface designs.

What is the operating voltage of the EPM9560RC210-20?

The EPM9560RC210-20 operates from a single 5V supply. According to the Altera MAX 9000 datasheet, VCCINT and VCCIO are both 5V on this variant, making it directly compatible with 5V TTL/CMOS logic. Newer MAX II/MAX V CPLDs typically operate at 3.3V or 1.8V core voltages.

Where to buy EPM9560RC210-20 online?

The EPM9560RC210-20 can be sourced from authorized distributors including DigiKey, Mouser, and Octopart-listed suppliers. Per Jotrin Electronics listing, the part is stocked in original-factory packaging. Pricing as of 2026-09-13 varies by quantity - expect approximately $60-$75 per unit at qty 1-10 with significant volume discounts at qty 100+. Verify RoHS3 compliance with the specific lot before ordering.

What is the lead time for EPM9560RC210-20 orders?

Per Alibaba supplier listings for EPM9560RC210-20, immediate delivery is available for Shenzhen and Hong Kong warehouses holding original-factory stock. Lead times from authorized distributors typically range from stock to 6-8 weeks depending on quantity. Because the part is in last-time-buy status, lead times can extend considerably for large orders - request a quote for bulk requirements.

EPM9560RC210-20 vs EPM9560RC208-20 - which is better for new designs?

The EPM9560RC210-20 and EPM9560RC208-20 are functionally equivalent in macrocells (560) and speed grade (-20 = 20ns tPD), differing only in package size. The RC210 (210-pin RQFP) provides more user I/O than the RC208 (208-pin RQFP). Per Altera's MAX 9000 datasheet, both share the same JTAG boundary-scan and 5V supply. For new designs, the RC208-20 is generally preferred for cost and PCB area savings unless more than ~164 I/O are required.

When should I choose EPM9560RC210-20 over an FPGA?

Choose the EPM9560RC210-20 over an FPGA when the design requires deterministic 20ns pin-to-pin timing, instant-on operation from non-volatile EEPROM (no boot PROM), and logic density up to 12,000 gates. Per the MAX 9000 datasheet, CPLD architectures like MAX 9000 offer more predictable timing and simpler PCB integration than FPGAs for glue-logic, bus-interface, and address-decoding applications. For designs needing above 50,000 gates, DSP blocks, or transceivers, an FPGA is more appropriate.

What is the best drop-in replacement for EPM9560RC210-20?

The best drop-in replacement for EPM9560RC210-20 is the EPM9560RC208-20 (208-pin RQFP, same 560 macrocells, same -20 speed grade) if 208-pin footprint is acceptable. According to the Altera MAX 9000 datasheet, same-family variants in compatible packages include the EPM9560RC208-20N and EPM9560RC208-20C. These parts are electrically and logically equivalent, differing only in pin count and operating temperature grade.

Can the EPM9560RC208-20 replace the EPM9560RC210-20?

Yes, the EPM9560RC208-20 can replace the EPM9560RC210-20 in most designs provided the PCB footprint can be modified from the 210-pin RQFP to the 208-pin RQFP. Per the Altera MAX 9000 datasheet, both share identical macrocell architecture (560 cells), 5V supply, and -20 speed grade. Because the packages differ in pin count, this is NOT a true drop-in replacement on the existing PCB - PCB redesign is required.

Where to download EPM9560 datasheet PDF?

The EPM9560 datasheet PDF is available from multiple sources including alldatasheet.com (530624/ALTERA/EPM9560), datasheet4u.com (Altera-Corporation/EPM9560/546622), and Altera's legacy documentation archives on Intel's website (Intel acquired Altera in 2015). Search for 'MAX 9000 datasheet' or 'EPM9560 datasheet' to retrieve the 46-page family datasheet covering electrical, timing, and package specifications.

Where to find EPM9560RC210-20 pinout?

The EPM9560RC210-20 pinout is documented in the Altera MAX 9000 family datasheet, which contains the 210-pin RQFP package pin assignment table. Per the datasheet, pins are numbered 1 to 210 around the RQFP package perimeter with dedicated JTAG (TCK, TMS, TDI, TDO) pins, dedicated global clock inputs, and 164-212 general-purpose user I/O. The MAX+PLUS II software auto-generates pin assignments during fitting.

What are the key specifications of EPM9560RC210-20 that engineers should know?

According to the Altera MAX 9000 datasheet, the EPM9560RC210-20 delivers 560 macrocells, 12,000 usable gates, 20ns tPD, 12ns tCO, 16 LABs of 36 macrocells each, 5V supply, JTAG boundary-scan, and approximately 164-212 user I/O in the 210-pin RQFP package. Built on 0.65um EEPROM, it offers in-system programmability via MAX+PLUS II. The part is RoHS3 compliant and currently in last-time-buy status as a mature Altera device.

工程参考数据： EPM9560RC210-20 ——对比、设计指导和合规信息。

选型指南

Choose EPM9560RC210-20 when your design needs the highest-density MAX 9000 CPLD with the maximum I/O count (164-212 pins) and a standard 20ns timing budget at the lowest cost. Choose EPM9560RC208-20 when your PCB can accept the 208-pin RQFP footprint - you save cost and PCB area while keeping identical logic density. Choose EPM9560RC208-15 when timing margin is critical and you can absorb the ~25% price premium for 15ns tPD. Avoid migrating to MAX 3000A or MAX 7000A in mid-design - the MAX 9000 architecture has dedicated global clock trees and JTAG support that those families lack. For new designs, consider MAX II or MAX V families which are still in active production; reserve EPM9560 for legacy sustainment.

与替代料对比

参数	本产品	EPM9560RC208-20	EPM9560RC208-20N	EPM9560RC208-20C	EPM9560RC208-21	EPM9560RC208-15
Package	RQFP-210	RQFP-208 (2 pins less)	RQFP-208	RQFP-208	RQFP-208	RQFP-208
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Macrocells	560	560	560	560	560	560
Usable Gates	12,000	12,000	12,000	12,000	12,000	12,000
Speed Grade (tPD)	20 ns	20 ns	20 ns	20 ns	21 ns (+5% slower)	15 ns (-25% faster)
Supply Voltage	5 V	5 V	5 V	5 V	5 V	5 V
Process Technology	0.65um EEPROM	0.65um EEPROM	0.65um EEPROM	0.65um EEPROM	0.65um EEPROM	0.65um EEPROM
JTAG Boundary-Scan	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1
Lifecycle Status	Last-time-buy (mature)	Last-time-buy	Last-time-buy	Last-time-buy	Last-time-buy	Last-time-buy
Approximate Unit Price (qty 100)	$65	$55 (est.)	$60 (est.)	$55 (est.)	$50 (est.)	$80 (est.)

关键差异点

Highest-density MAX 9000 device with 560 macrocells （对比 EPM9480RC208-15)
210-pin RQFP package for maximum I/O count （对比 EPM9560RC208-20)
-20 speed grade offers balanced performance/cost （对比 EPM9560RC208-15)
Mature production status with proven long-term supply （对比 EPM9560ARC208-10)

设计说明

The 210-pin RQFP package uses 0.5mm lead pitch with a body size of approximately 32mm x 32mm. Per Altera MAX 9000 PCB layout guidelines, allocate at least 4-layer PCB with continuous ground plane under the device to control switching noise. Use micro-via or via-in-pad if design rules allow, otherwise place ground vias in the land pattern area. Decoupling: at least four 0.1uF ceramic + one 10uF tantalum per VCC pin group, placed within 5mm of each VCC pin.

The EPM9560RC210-20 draws ICC of approximately 200-400 mA depending on logic utilization and toggle rate. Per Altera datasheet, unused I/O pins should be configured as outputs driving ground or defined inputs with pull-ups to minimize supply current. The 5V supply ramp must be monotonic; if not, hold OE low until VCC reaches 4.75V to prevent output buffer latch-up. Add a supervisory reset circuit to ensure clean power-up.

Global clock pins (GLOBAL_CLK) and global output-enable pins (GLOBAL_OE) must be assigned to dedicated package pins per the Altera MAX+PLUS II fitting report. These pins route directly to the LAB clock and OE trees - using them as user I/O loses the deterministic global-signal advantage. Keep high-speed clock traces short (<25mm) and impedance-matched (50 ohms) to avoid ringing. JTAG chain pins (TCK, TMS, TDI, TDO) require 10k pull-ups on TMS and TDI per IEEE 1149.1.