EPM9560RI208-15N vs EPM9560RI208-10 对比

详细并排对比 EPM9560RI208-15N 出自 Altera 和 EPM9560RI208-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI208-15N EPM9560RI208-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $19.45 $67.80
Manufacturer Altera (Intel Programmable Solutions Group) —
Device Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX), 3rd generation —
Configuration Memory CMOS EEPROM, in-system programmable EEPROM, 100 erase/program cycles
封装 208-pin RQFP (Ruggedized Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Total Pins 356 (per third-party catalog; see _validation_note) —
Package Pin Count 208 —
Terminal Form Gull Wing —
Package Code HFQFP —
User I/Os 216 (per DigiChip specification; see _validation_note) —
Maximum Internal Frequency 145 MHz —
Propagation Delay (tPD) 11.4 ns (15 ns speed grade) —
Speed Grade -15 —
电源电压 5.0 V —
工作温度 0C to 70C (Commercial) -40 °C to +85 °C (Industrial)
Temperature Grade Industrial (per Vyrian/Partstack listings) —
Logic Family CMOS —
Programming Interface IEEE 1149.1 JTAG, 5.0-V in-system IEEE 1149.1 (JTAG) / ISP
RoHS 状态 [DATA_NEEDED: RoHS status] ROHS3 Compliant
Family — MAX 9000
Usable Gates — 12,000
Macrocells — 560
Logic Array Blocks (LABs) — [DATA_NEEDED: LAB count]
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency — 144 MHz
Supply Voltage (VCCINT) — 5.0 V
User I/O Pins — 212 (typical for 208-RQFP package)
安装类型 — Surface Mount
湿敏等级(MSL) — 3 (168 Hours)
Lead Time — 1-7 days (per fpgalink listing)

数据手册与资源

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