EPM9560RI208-15N vs EPM9560RI208-10 Comparison
Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9560RI208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-15N | EPM9560RI208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.45 | $67.80 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Device Family | MAX 9000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | β |
| Configuration Memory | CMOS EEPROM, in-system programmable | EEPROM, 100 erase/program cycles |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | β |
| Package Pin Count | 208 | β |
| Terminal Form | Gull Wing | β |
| Package Code | HFQFP | β |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | β |
| Maximum Internal Frequency | 145 MHz | β |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | β |
| Speed Grade | -15 | β |
| Supply Voltage | 5.0 V | β |
| Operating Temperature | 0C to 70C (Commercial) | -40 Β°C to +85 Β°C (Industrial) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | β |
| Logic Family | CMOS | β |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | IEEE 1149.1 (JTAG) / ISP |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Family | β | MAX 9000 |
| Usable Gates | β | 12,000 |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 144 MHz |
| Supply Voltage (VCCINT) | β | 5.0 V |
| User I/O Pins | β | 212 (typical for 208-RQFP package) |
| Mounting Type | β | Surface Mount |
| Moisture Sensitivity Level (MSL) | β | 3 (168 Hours) |
| Lead Time | β | 1-7 days (per fpgalink listing) |