EPM9560RI240-15N vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RI240-15N 出自 Intel 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI240-15N EPM9560RC240-15N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $27.85
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Logic Family MAX 9000 (Multiple Array MatriX) CMOS (EEPROM-based)
Macrocells 560 560
Flip-Flops 772 —
Usable Gates 12,000 12,000
User I/O Pins 216 —
封装 240-pin RQFP (PowerQuad Flat Pack) RQFP-240 (240-pin Plastic Quad Flat Pack)
Pin-to-Pin Propagation Delay 15 ns —
Internal Frequency 145 MHz —
电源电压 5.0 V 5.0 V
I/O Voltage Compatibility 3.3 V or 5.0 V configurable —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE 1149.1 (JTAG) boundary scan —
工作温度范围 -40 C to +85 C (industrial) —
安装类型 Surface Mount Surface Mount
RoHS 状态 RoHS3 Compliant [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Moisture Sensitivity Level MSL 3 (168 hours) —
Manufacturer Standard Lead Time 1-7 days (distributor stock) —
Series — MAX 9000
Family — MAX 9000 (third-generation Multiple Array MatriX)
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)
工作温度 — 0C to +70C (Commercial)

数据手册与资源

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