MC9S12E64MPVE vs MC9S12E64CPVE 对比
详细并排对比 MC9S12E64MPVE 出自 NXP Semiconductors 和 MC9S12E64CPVE 出自 NXP Semiconductors。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | MC9S12E64MPVE | MC9S12E64CPVE |
|---|---|---|
| 品牌 | NXP Semiconductors | NXP Semiconductors |
| 分类 | Microcontrollers | Microcontrollers |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.55 | $0.00 |
| Core | HCS12 (16-bit CISC) | HCS12 |
| Program Memory (Flash) | 64 KB (64K x 8) | — |
| RAM Size | 4 KB (4K x 8) | — |
| Maximum CPU Clock / Bus Speed | 25 MHz | — |
| 工作电源电压 | 2.5 V / 3.3 V / 5 V | — |
| Number of I/O | 92 | — |
| 封装 / 外壳 | 112-LQFP (20 x 20 mm) | — |
| 安装类型 | Surface Mount | — |
| Terminal Form | GULL WING | Gull wing |
| Number of Terminals | 112 | — |
| Package Shape | SQUARE | — |
| Temperature Grade | Automotive (per Partstack listing) | Industrial |
| CAN Controllers | Up to 2 x MSCAN (CAN 2.0A/B) [DATA_NEEDED: exact count per mask] | — |
| ADC | 8-channel, 10-bit [DATA_NEEDED: channels per mask set] | — |
| PWM | 8-channel [DATA_NEEDED: resolution] | — |
| Debug Interface | Background Debug Mode (BDM) | — |
| RoHS 状态 | Compliant (per ETEI comparison) | — |
| REACH Status | Compliant (per ETEI comparison) | — |
| Series | HCS12 | — |
| Product Type | — | 16-bit HCS12 microcontroller |
| Maximum Core Frequency | — | 25 MHz |
| Flash Memory | — | 64 KB |
| Data Bus | — | 16-bit |
| 封装 | — | 112-pin LQFP, 20 mm x 20 mm |
| Package Type | — | LQFP |
| Phase-Locked Loop | — | On-chip PLL |
| Voltage Regulator | — | On-chip bandgap-based voltage regulator |
| Product Series | — | HCS12 / MC9S12E |
| Manufacturer | — | NXP Semiconductors |
| 生命周期状态 | — | NRND |
| RoHS | — | [DATA_NEEDED: RoHS status] |
| REACH | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| 电源电压 | — | [DATA_NEEDED: supply voltage range] |
| RAM | — | [DATA_NEEDED: RAM size] |
| External Memory Interface | — | [DATA_NEEDED: external memory interface details] |