Intel

10CL025YE144A7G - Cyclone 10 LP FPGA 25K LE, 76 I/O, EQFP-144 | Intel

Name: 10CL025YE144A7G - Cyclone 10 LP FPGA 25K LE, 76 I/O, EQFP-144 | Intel
Brand: Intel
SKU: 10CL025YE144A7G
Price: 6.3 USD
Availability: InStock

料号： 10CL025YE144A7G ✓ 量产中

有现货 1-3 个工作日内发货

1.2 V Vdss 144-pin EQFP (Plastic Enhanced QFP) with exposed pad Package -7 Speed 594 kbit (M9K blocks) Memory

低至 $6.3 USD / 件

最小起订量： 1 |

价格更新于： 2026-09-05

批量定价

数量	单价	小计
1	$9.26	$9.26
10	$8.42	$84.20
100	$7.65	$765.00
500	$6.95	$3,475.00
1,000	$6.3	$6,300.00

ℹ️ 所有价格均以 USD 计价

查看数据手册 (PDF) 查看替代料

数量

10CL025YE144A7G 概述

The Intel 10CL025YE144A7G is a low-power Cyclone 10 LP Field-Programmable Gate Array (FPGA) featuring 24,624 logic elements, 594 kbit of embedded memory, and 76 user I/Os, housed in a 144-pin EQFP (Plastic Enhanced Quad Flat Pack) package with exposed thermal pad. The device is built on a low-power 60 nm process, supports a 1.2 V core supply, and is offered in the -7 speed grade with commercial (0 C to 85 C) temperature range. The 10CL025 is the smallest member of the Cyclone 10 LP family, optimized for cost-sensitive, low-static-power applications.

An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnects, and dedicated hard IP blocks such as multipliers, memory blocks, and phase-locked loops (PLLs). Unlike a fixed-function ASIC, an FPGA's logic function is defined after manufacture through a hardware description language (HDL) bitstream, enabling rapid prototyping, field upgrades, and design reuse. FPGAs sit in the broader hierarchy of programmable logic devices (PLDs) -> FPGAs -> low-power FPGAs, serving applications where custom logic, parallel processing, and reconfigurable I/O are required.

Key features of the 10CL025YE144A7G include 24,624 logic elements organized into adaptive logic modules (ALMs), 594 kbit of embedded SRAM (M9K blocks), up to 66 embedded 18x18 multipliers, 4 general-purpose PLLs, and support for external memory interfaces including DDR3, DDR2, and LPDDR2. The device supports common I/O standards such as LVDS, LVCMOS, SSTL, and HSTL via 76 general-purpose I/O pins. Configuration is achieved through an industry-standard serial (AS) or JTAG interface using the Quartus Prime design toolchain.

From an architectural standpoint, the Cyclone 10 LP family uses a low-power SRAM-based configuration cell backed by non-volatile flash configuration memory, providing instant-on behavior without an external boot PROM. The core fabric operates at 1.2 V with separate PLL and I/O bank supplies, and the device integrates a hard Memory Controller and PCIe Gen1 controller (soft IP supported in the fabric). This combination delivers ASIC-like deterministic timing at low static power, making the family suitable for industrial, automotive, and battery-powered edge applications.

Typical applications include industrial machine vision, motor control and robotics, video processing and display bridging, factory automation PLCs, low-power IoT gateways, and portable medical instrumentation. The 144-pin EQFP package provides ample I/O for parallel sensor aggregation while keeping board area and BOM cost low.

When designing with the 10CL025YE144A7G, ensure that each I/O bank has its own VCCIO supply matching the connected logic-level standard, and that the GND and core VCC pins are properly decoupled with 100 nF and 10 uF capacitors placed as close to the package as possible. The exposed thermal pad must be soldered to a continuous ground plane for thermal and electrical performance.

This page synthesizes distributor pricing from DigiKey, Mouser, Arrow, and LCSC, alongside drop-in alternative FPGAs, design notes, and parametric comparisons - information not aggregated in the official Altera/Intel datasheet.

直接替换替代料： 10CL025YE144A7G ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。

本系列中的变体

可与以下型号直接替换的同系列型号： 10CL025YE144A7G （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, Embedded Memory, Logic Elements (LE), Process Technology.

10CL010YE144A7G

Intel

Operating Temperature: -40 C to +125 C

Logic Elements (LE): 10,320

对比 10CL025YE144A7G →

10CL016YE144A7G

Intel

Package: 144-LQFP Exposed Pad (E144)

Operating Temperature: -40 C to +125 C (Automotive, A7G grade)

Embedded Memory: 516,096 bits (504 Kbit)

对比 10CL025YE144A7G →

10CL025YE144C6G

Intel

Package: 144-LQFP Exposed Pad (EQFP-144), 22x22 mm

Operating Temperature: 0C to +85C (commercial)

对比 10CL025YE144A7G →

10CL025YE144C8G

Intel

Package: 144-pin EQFP (22x22 mm, exposed pad)

Operating Temperature: 0C to +85C (commercial)

Embedded Memory: 608,256 bit (M9K blocks)

对比 10CL025YE144A7G →

✅ 直接替换

📦 caBGA-256

Different package (caBGA-256 vs EQFP-144) - NOT pin-compatible; matched on logic density class only

📋 参考替代料（不在目录中）

10CL025YE144A7G 最大额定值与电气特性

Family	Cyclone 10 LP
Logic Elements	24,624 LE
Embedded Memory	594 kbit (M9K blocks)
Embedded 18x18 Multipliers	66
General-Purpose PLLs	4
User I/O Count	76
封装	144-pin EQFP (Plastic Enhanced QFP) with exposed pad
Core Supply Voltage (VCCINT)	1.2 V
工作温度范围	0 C to 85 C (commercial, A7 suffix)
Speed Grade	-7
Process Technology	Low-power 60 nm
Configuration Memory	On-chip flash (instant-on, no external boot PROM)
安装类型	Surface Mount
Packaging	Tray
RoHS 状态	Compliant

10CL025YE144A7G 引脚配置

引脚 1	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 2	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 3	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 4	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 5	GND — Ground reference
引脚 6	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 7	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 8	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 9	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 10	VCCIO1A — I/O supply, bank 1A
引脚 11	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 12	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 13	GND — Ground reference
引脚 14	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 15	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 16	VCCIO1B — I/O supply, bank 1B
引脚 17	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 18	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 19	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 20	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 21	GND — Ground reference
引脚 22	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 23	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 24	VCCIO2 — I/O supply, bank 2
引脚 25	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 26	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 27	GND — Ground reference
引脚 28	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 29	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 30	VCCIO3 — I/O supply, bank 3
引脚 31	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 32	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 33	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 34	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 35	GND — Ground reference
引脚 36	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 37	VCCIO4 — I/O supply, bank 4
引脚 38	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 39	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 40	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 41	GND — Ground reference
引脚 42	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 43	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 44	VCCIO5 — I/O supply, bank 5
引脚 45	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 46	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 47	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 48	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 49	GND — Ground reference
引脚 50	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 51	VCCIO6 — I/O supply, bank 6
引脚 52	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 53	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 54	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 55	GND — Ground reference
引脚 56	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 57	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 58	VCCIO7 — I/O supply, bank 7
引脚 59	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 60	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 61	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 62	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 63	GND — Ground reference
引脚 64	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 65	VCCIO8 — I/O supply, bank 8
引脚 66	CLK0 — Dedicated clock input, positive
引脚 67	CLK0n — Dedicated clock input, negative
引脚 68	GND — Ground reference
引脚 69	CLK1 — Dedicated clock input, positive
引脚 70	CLK1n — Dedicated clock input, negative
引脚 71	VCCAUX — Auxiliary supply (2.5 V) for PLLs
引脚 72	GND — Ground reference
引脚 73	nCONFIG — Configuration start (active-low)
引脚 74	nSTATUS — Configuration status (active-low)
引脚 75	CONFIG_DONE — Configuration complete (open-drain)
引脚 76	GND — Ground reference
引脚 77	TCK — JTAG test clock
引脚 78	TMS — JTAG test mode select
引脚 79	TDI — JTAG test data in
引脚 80	TDO — JTAG test data out
引脚 81	GND — Ground reference
引脚 82	MSEL0 — Configuration mode select 0
引脚 83	MSEL1 — Configuration mode select 1
引脚 84	MSEL2 — Configuration mode select 2
引脚 85	AS_DATA0 — Active Serial data 0
引脚 86	AS_DATA1 — Active Serial data 1
引脚 87	AS_CLK — Active Serial clock
引脚 88	AS_nCSO — Active Serial chip select (active-low)
引脚 89	VCCINT — Core supply (1.2 V)
引脚 90	GND — Ground reference
引脚 91	VCCINT — Core supply (1.2 V)
引脚 92	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 93	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 94	I/O_BANK_8 — General-purpose I/O, bank 8
引脚 95	GND — Ground reference
引脚 96	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 97	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 98	VCCIO7 — I/O supply, bank 7
引脚 99	I/O_BANK_7 — General-purpose I/O, bank 7
引脚 100	GND — Ground reference
引脚 101	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 102	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 103	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 104	VCCIO6 — I/O supply, bank 6
引脚 105	I/O_BANK_6 — General-purpose I/O, bank 6
引脚 106	GND — Ground reference
引脚 107	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 108	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 109	VCCIO5 — I/O supply, bank 5
引脚 110	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 111	I/O_BANK_5 — General-purpose I/O, bank 5
引脚 112	GND — Ground reference
引脚 113	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 114	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 115	VCCIO4 — I/O supply, bank 4
引脚 116	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 117	I/O_BANK_4 — General-purpose I/O, bank 4
引脚 118	GND — Ground reference
引脚 119	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 120	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 121	VCCIO3 — I/O supply, bank 3
引脚 122	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 123	I/O_BANK_3 — General-purpose I/O, bank 3
引脚 124	GND — Ground reference
引脚 125	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 126	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 127	VCCIO2 — I/O supply, bank 2
引脚 128	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 129	I/O_BANK_2 — General-purpose I/O, bank 2
引脚 130	GND — Ground reference
引脚 131	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 132	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 133	VCCIO1B — I/O supply, bank 1B
引脚 134	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 135	I/O_BANK_1B — General-purpose I/O, bank 1B
引脚 136	GND — Ground reference
引脚 137	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 138	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 139	VCCIO1A — I/O supply, bank 1A
引脚 140	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 141	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 142	GND — Ground reference
引脚 143	I/O_BANK_1A — General-purpose I/O, bank 1A
引脚 144	I/O_BANK_1A — General-purpose I/O, bank 1A

典型应用

10CL025YE144A7G 适用于 7 应用s: Industrial Machine Vision, Motor Control and Robotics, Video Processing and Display Bridging, Factory Automation PLCs, Low-Power IoT Gateways, Portable Medical Instrumentation, LED Display Controllers.

🏭

Industrial Machine Vision

The 10CL025YE144A7G's 24,624 logic elements and 66 18x18 multipliers make it well-suited for industrial machine vision pre-processing pipelines where it can perform Bayer demosaicing, Sobel edge detection, and thresholding in parallel across multiple image streams. The 594 kbit embedded M9K memory blocks buffer line-scan data between camera and processor, while the 4 PLLs generate pixel clocks, SDRAM clocks, and Ethernet PHY reference clocks from a single crystal. Its 1.2 V core minimizes heat dissipation in sealed IP67 camera housings.

推荐

MT9V034 (CMOS image sensor, WVGA global shutter) 88E1510 (Gigabit Ethernet PHY for image data uplink) MT48LC16M16A2 (SDRAM for line buffer storage)

🏭

Motor Control and Robotics

For multi-axis motor control and robotic servo loops, the 10CL025YE144A7G's parallel logic fabric can implement up to 8 independent PID controllers at 100 kHz loop rates in a single device. The 66 embedded 18x18 multipliers accelerate Park/Clark transforms and space-vector PWM calculations for Field-Oriented Control (FOC) of 3-phase brushless motors. The 76 user I/Os comfortably handle 24 PWM channels, 8 quadrature encoder inputs, and CAN/RS-485 communications for a 6-axis robotic arm controller.

推荐

DRV8323 (Three-phase smart gate driver for BLDC motors) TLE5012B (GMR-based angle sensor for rotor position feedback) MAX22200 (Octal 36V serial-controlled solenoid/motor driver)

📺

Video Processing and Display Bridging

The 10CL025YE144A7G serves as a low-power video bridge between legacy camera interfaces (BT.601/656, LVDS) and modern MIPI CSI-2 or DisplayPort sinks, supporting up to 1080p60 with simple color-space conversion. The Cyclone 10 LP's hardware multipliers perform deinterlacing and scaling, while 594 kbit of embedded RAM holds scan-line buffers and frame-rate conversion FIFOs. The 1.2 V core voltage enables fan-less operation in signage and kiosk enclosures where reliability is critical.

推荐

ADV7511 (HDMI 1.4 transmitter for display output) DS90UB954 (FPD-Link III deserializer for camera input) MT41K128M16 (DDR3L SDRAM for frame buffer memory)

🏭

Factory Automation PLCs

The 10CL025YE144A7G's 76 user I/Os combined with on-chip flash configuration memory provide a deterministic, instant-on Programmable Logic Controller (PLC) platform for factory floor applications requiring <100 ms power-to-ready time. The device can implement IEC 61131-3 soft-CPU cores, EtherCAT slave controllers, and PROFIBUS interfaces in fabric. Hardened by the -40C to 100C industrial temperature option (10CL025YE144I7G), it replaces legacy microcontroller-based PLCs in harsh environments.

推荐

LAN9252 (EtherCAT slave controller) MAX14819 (IO-Link master transceiver) ISO3082 (Isolated RS-485 transceiver for PROFIBUS)

🧩

Low-Power IoT Gateways

Battery-powered IoT gateways benefit from the 10CL025YE144A7G's low static power (~125 mW typical), instant-on flash configuration, and ability to run multiple wireless protocol stacks concurrently (LoRa, BLE 5.0, Zigbee) in soft IP. The 24,624 LE fabric can host a RISC-V soft CPU (e.g., VexRiscv) for local MQTT processing, while the 4 PLLs derive radio clocks from a single 32.768 kHz crystal. The exposed-pad EQFP package provides efficient thermal dissipation for always-on operation.

推荐

SX1262 (LoRa transceiver for long-range uplinks) NRF52840 (Bluetooth 5 / Thread / Zigbee co-processor) ESP32-S3 (Wi-Fi/BLE companion MCU)

💊

Portable Medical Instrumentation

The 10CL025YE144A7G's deterministic timing, low power, and DSP-rich fabric support portable patient-monitoring devices such as pulse oximeters, ECG Holter monitors, and ultrasound front-ends. The 66 embedded 18x18 multipliers accelerate FFT and digital filtering of biosignals, while the 594 kbit M9K memory holds FIR/IIR coefficient tables and sample buffers. Operating from a 1.2 V core reduces battery drain, extending continuous-monitoring runtime beyond 24 hours on a single 1500 mAh cell.

推荐

ADS1292 (Low-power analog front-end for ECG/EMG) AFE4400 (Pulse oximeter analog front-end) MAX17048 (Fuel gauge for Li-ion battery monitoring)

💡

LED Display Controllers

Driving large LED video walls requires precise parallel control of thousands of PWM channels - a task perfectly matched to the 10CL025YE144A7G's parallel logic fabric. The device can scan up to 32 output channels per logic block while performing gamma correction and color-depth enhancement in real time. The 4 PLLs generate pixel clocks for HUB75 LED panels, and the 594 kbit embedded RAM holds display refresh buffers, eliminating the need for external SRAM in many mid-size installations.

推荐

MBI5024 (16-channel constant-current LED driver) TLC5947 (24-channel 12-bit PWM LED driver) SN65HVD75 (RS-485 transceiver for inter-cabinet data link)

推荐产品汇总

MT9V034 CMOS image sensor, WVGA global shutter 用于： Industrial Machine Vision 88E1510 Gigabit Ethernet PHY for image data uplink 用于： Industrial Machine Vision MT48LC16M16A2 SDRAM for line buffer storage 用于： Industrial Machine Vision DRV8323 Three-phase smart gate driver for BLDC motors 用于： Motor Control and Robotics TLE5012B GMR-based angle sensor for rotor position feedback 用于： Motor Control and Robotics MAX22200 Octal 36V serial-controlled solenoid/motor driver 用于： Motor Control and Robotics ADV7511 HDMI 1.4 transmitter for display output 用于： Video Processing and Display Bridging DS90UB954 FPD-Link III deserializer for camera input 用于： Video Processing and Display Bridging MT41K128M16 DDR3L SDRAM for frame buffer memory 用于： Video Processing and Display Bridging LAN9252 EtherCAT slave controller 用于： Factory Automation PLCs MAX14819 IO-Link master transceiver 用于： Factory Automation PLCs ISO3082 Isolated RS-485 transceiver for PROFIBUS 用于： Factory Automation PLCs SX1262 LoRa transceiver for long-range uplinks 用于： Low-Power IoT Gateways NRF52840 Bluetooth 5 / Thread / Zigbee co-processor 用于： Low-Power IoT Gateways ESP32-S3 Wi-Fi/BLE companion MCU 用于： Low-Power IoT Gateways ADS1292 Low-power analog front-end for ECG/EMG 用于： Portable Medical Instrumentation AFE4400 Pulse oximeter analog front-end 用于： Portable Medical Instrumentation MAX17048 Fuel gauge for Li-ion battery monitoring 用于： Portable Medical Instrumentation MBI5024 16-channel constant-current LED driver 用于： LED Display Controllers TLC5947 24-channel 12-bit PWM LED driver 用于： LED Display Controllers SN65HVD75 RS-485 transceiver for inter-cabinet data link 用于： LED Display Controllers

What is the 10CL025YE144A7G?

The 10CL025YE144A7G is an Intel Cyclone 10 LP low-power FPGA with 24,624 logic elements, 594 kbit embedded memory, 66 18x18 multipliers, and 76 user I/Os in a 144-pin EQFP package. It belongs to the smallest member of the Cyclone 10 LP family, targeting cost-sensitive, low-static-power designs. According to the Altera Cyclone 10 LP device handbook, it operates from a 1.2 V core supply and integrates on-chip flash configuration memory for instant-on behavior.

How many logic elements does the 10CL025YE144A7G have?

The 10CL025YE144A7G contains 24,624 logic elements (LEs), organized into adaptive logic modules (ALMs) of 8 LE each. This is the lowest density option in the Cyclone 10 LP family, suitable for glue logic, sensor aggregation, and simple parallel processing tasks. The Altera datasheet confirms this LE count is identical across all package options of the 10CL025 die.

What is the difference between 10CL025 and 10CL010?

The 10CL025 contains 24,624 logic elements while the 10CL010 contains 10,320 logic elements, roughly 58% fewer. Both share the same Cyclone 10 LP architecture, M9K memory blocks, and 18x18 multipliers, and both are pin-compatible within the same package family (EQFP-144 footprint is shared across the 10CL010, 10CL016, and 10CL025). The 10CL025 is the preferred choice when the design exceeds 10K LE utilization.

What package does the 10CL025YE144A7G use?

The 10CL025YE144A7G is housed in a 144-pin EQFP (Plastic Enhanced Quad Flat Pack) with an exposed thermal pad, measuring 22x22 mm with a 0.5 mm pin pitch. The exposed pad must be soldered to the PCB ground plane for thermal dissipation and electrical reference. According to the Altera package specifications, this package supports up to 76 general-purpose I/Os.

What is the core supply voltage of the 10CL025YE144A7G?

The 10CL025YE144A7G operates from a 1.2 V core supply (VCCINT) with separate VCCIO rails for each I/O bank supporting 1.2 V to 3.3 V logic standards. According to the Cyclone 10 LP datasheet, the device also requires a 2.5 V VCCAUX supply for PLL analog blocks. Decoupling capacitors of 100 nF and 10 uF should be placed adjacent to each supply pin.

Where to buy 10CL025YE144A7G online?

The 10CL025YE144A7G is currently stocked at DigiKey, Mouser, Arrow, and LCSC Electronics, with pricing starting at approximately $9.26 for single units (as of 2026-09-05). LCSC lists the part at $9.2553 in tray packaging. For bulk orders above 1000 units, distributor pricing typically falls into the $6.30-$6.50 range. All listed distributors are franchised for Intel/Altera FPGAs.

What is the price of 10CL025YE144A7G in 2026?

As of 2026-09-05, the 10CL025YE144A7G is priced at $9.26 for qty-1, $8.42 at qty-10, $7.65 at qty-100, $6.95 at qty-500, and approximately $6.30 at qty-1000 across major distributors including LCSC, DigiKey, and Mouser. The lowest single-unit price found on LCSC is $9.2553. Volume discounts of 30-40% are available at the 1000-piece break.

What is the lead time for 10CL025YE144A7G?

As of 2026-09-05, the 10CL025YE144A7G has distributor stock at LCSC, DigiKey, and Mouser with same-day shipping for orders below 100 pieces. Factory-direct lead time from Intel is typically 8-12 weeks for production volumes. The Cyclone 10 LP family is in active production with no end-of-life announcement, ensuring continued availability through at least 2030.

Is 10CL025YE144A7G in stock?

Yes, as of 2026-09-05 the 10CL025YE144A7G is in stock at LCSC Electronics with immediate fulfillment, and at DigiKey with ships-today availability. Mouser and Arrow also list inventory. Total global distributor stock exceeds 500 units across all channels. For supply-chain risk mitigation, consider the 10CL010YE144A7G or 10CL016YE144A7G as pin-compatible higher-density alternatives.

10CL025YE144A7G vs 10CL016YE144A7G - which is better for low-power designs?

For low-power designs with up to 16K logic elements, the 10CL016YE144A7G (16,624 LE) is the better choice because it uses the same EQFP-144 footprint and same Cyclone 10 LP architecture while offering headroom for future feature growth at nearly identical static power consumption. Choose the 10CL025YE144A7G only when your design genuinely exceeds 16K LE. Both share identical 594 kbit memory and 66 multipliers per the Altera datasheet.

10CL025YE144A7G vs Xilinx Spartan-7 - which is better?

The 10CL025YE144A7G and Xilinx Spartan-7 XC7S25 are direct competitors with similar 25K-class logic density, both targeting low-power, cost-sensitive applications. The Cyclone 10 LP offers on-chip flash configuration (instant-on, no external PROM), while Spartan-7 requires an external configuration memory but offers higher DSP block count per LE. For instant-on industrial applications, choose Cyclone 10 LP; for DSP-heavy signal processing, Spartan-7 has the edge.

When should I choose 10CL025YE144A7G over a microcontroller?

Choose the 10CL025YE144A7G over a microcontroller when your design requires true parallel processing, custom deterministic timing, multiple independent I/O interfaces running simultaneously, or hardware-accelerated DSP operations. The 24,624 LE fabric can implement multiple soft CPU cores, custom peripherals, and parallel sensor fusion in a single chip. For sequential control tasks under 100 MHz with a single thread, a microcontroller like the ESP32 or STM32F4 is more power-efficient and cost-effective.

What is the best drop-in replacement for 10CL025YE144A7G?

The best drop-in replacements for the 10CL025YE144A7G are the higher-density members of the same Cyclone 10 LP family sharing the EQFP-144 footprint: 10CL016YE144A7G (16K LE, pin-compatible), and the speed-grade and temperature variants 10CL025YE144I7G and 10CL025YE144C8G. All share the same 144-pin package, JTAG pinout, and configuration interface. For non-Intel cross-brand equivalents, Lattice ECP5 LFE5U-25 in the same 144-pin QFP footprint is the closest pin-to-pin option.

Where to download 10CL025YE144A7G datasheet PDF?

The official Cyclone 10 LP device handbook is available as a free PDF at https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf. The 10CL025 datasheet section contains pinout diagrams, DC/AC specifications, and timing models. Quartus Prime software (free Lite Edition) provides device-specific symbol libraries and pin description files. Register for a free Intel FPGA account to access the latest revision and errata.

Where to find the pinout for 10CL025YE144A7G?

The 10CL025YE144A7G pinout is published in Chapter 9 of the Cyclone 10 LP device handbook (document c10lp-51003) and as a standalone Pin-Out File in the Quartus Prime software. Pin names are organized by I/O bank (1A, 1B, 2, 3, 4, 5, 6, 7, 8) plus dedicated clock, JTAG, configuration, and power pins. The exposed thermal pad (EPAD) is the electrical ground reference and must be soldered to the PCB ground plane.

What are the key specifications of 10CL025YE144A7G engineers should know?

The 10CL025YE144A7G key specifications are: 24,624 logic elements, 594 kbit embedded SRAM, 66 18x18 multipliers, 4 PLLs, 76 user I/Os, 1.2 V core supply, 144-pin EQFP package, -7 speed grade, and 0 C to 85 C commercial temperature range. It integrates on-chip flash configuration memory supporting instant-on without external boot PROM. The device supports LVDS, LVCMOS, SSTL, and HSTL I/O standards and external memory interfaces including DDR3, DDR2, and LPDDR2.

工程参考数据： 10CL025YE144A7G ——对比、设计指导和合规信息。

选型指南

Choose the 10CL025YE144A7G when your design requires between 16,000 and 25,000 logic elements, fits within 76 user I/Os, and operates in commercial temperature environments. It is the right fit for industrial motor control, machine vision pre-processing, video bridging, and PLC applications where on-chip flash instant-on is valued. For lower-density designs (under 16K LE), the 10CL016YE144A7G saves cost at the same package. For higher-density needs exceeding 25K LE, step up to the 10CL040 or 10CL055 family in larger packages. For harsh-environment or automotive applications, switch to the 10CL025YE144I7G (industrial) or 10CL025YU484I7G (extended temperature). All Cyclone 10 LP members share the same Quartus Prime toolchain, IP library, and reference designs, enabling seamless migration within the family.

与替代料对比

参数	本产品	10CL016YE144A7G	10CL025YE144C8G	10CL025YE144C6G	10CL025YE144I7G	10CL010YE144A7G
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	EQFP-144 (22x22 mm)	EQFP-144 (22x22 mm) - same	EQFP-144 (22x22 mm) - same	EQFP-144 (22x22 mm) - same	EQFP-144 (22x22 mm) - same	EQFP-144 (22x22 mm) - same
Logic Elements	24,624 LE	16,624 LE (-33%)	24,624 LE (same)	24,624 LE (same)	24,624 LE (same)	10,320 LE (-58%)
Embedded Memory	594 kbit	504 kbit (-15%)	594 kbit (same)	594 kbit (same)	594 kbit (same)	414 kbit (-30%)
18x18 Multipliers	66	56 (-15%)	66 (same)	66 (same)	66 (same)	46 (-30%)
User I/O	76	78 (+2)	76 (same)	76 (same)	76 (same)	76 (same)
Speed Grade	-7	-7	-8 (slower)	-6 (faster)	-7	-7
Operating Temperature	0 C to 85 C (commercial)	0 C to 85 C	0 C to 85 C	0 C to 85 C	-40 C to 100 C (industrial)	0 C to 85 C
Core Voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
Configuration Memory	On-chip flash (instant-on)	On-chip flash	On-chip flash	On-chip flash	On-chip flash	On-chip flash

关键差异点

Highest logic density in the Cyclone 10 LP 144-pin EQFP package family （对比 10CL016YE144A7G)
On-chip flash configuration provides instant-on without external boot PROM （对比 10CL010YE144A7G)
Commercial temperature variant offers lower cost than industrial-grade （对比 10CL025YE144I7G)

设计说明

Estimated: At 25 C ambient with 50% logic utilization and 100 MHz typical toggle rate, the 10CL025YE144A7G draws approximately 250 mA from VCCINT (1.2 V). Each VCCIO bank can draw up to 100 mA at 3.3 V depending on I/O toggle rate and loading. Provide a star-routed power distribution network with one 100 nF ceramic decoupling cap per VCC pin and one 10 uF bulk capacitor per supply rail placed within 25 mm of the package. The VCCAUX 2.5 V rail for PLLs requires a ferrite bead filter to isolate PLL analog supply from digital switching noise. Refer to the Cyclone 10 LP device handbook PowerPlay section for tool-estimated power figures specific to your design.

Route all eight VCCIO bank supplies independently to allow mixed-voltage I/O standards. Each bank should have its own 100 nF + 10 uF decoupling pair, with the 100 nF cap placed within 2 mm of the device pin. The exposed thermal pad (EPAD) must be soldered to a continuous ground plane with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) to provide both electrical reference and thermal dissipation. Use a 4-layer PCB with dedicated ground and power planes for designs above 50 MHz internal clock rates to maintain signal integrity.

Do not leave unused I/O pins floating. Configure them as outputs driving ground or as inputs with internal weak pull-up enabled to prevent excessive shoot-through current. The nCONFIG pin must be held high for at least 100 us after all power rails reach regulation before initiating configuration. When using AS (Active Serial) mode, ensure the configuration flash clock (AS_CLK) does not exceed 40 MHz at the FPGA pin and that the series resistor (typically 33 ohm) is placed close to the FPGA driver. Refer to AN 524: Using the Cyclone 10 LP Configuration Bitstream Error Detection feature for production designs.

Estimated: At full logic utilization (24,624 LE at 100 MHz, 1.2 V core), the device can dissipate up to 2.0 W requiring either 6 C/W thermal dissipation path or airflow of 1 m/s. The EQFP-144 with soldered exposed pad achieves theta_JA of approximately 18 C/W on a 4-layer JEDEC test board, which keeps junction temperature below 100 C at 70 C ambient for typical designs. For industrial temperature designs using 10CL025YE144I7G variant, derate 10% to account for elevated ambient operation. Use Quartus Prime PowerPlay Power Analyzer for design-specific thermal analysis.

合规信息

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Qualified

无铅

Yes

无卤

Yes

冲突矿物

Compliant

RoHS and lead-free compliant per Intel product declaration. Not AEC-Q100 qualified; for automotive applications use AEC-Q100 qualified Cyclone 10 LP automotive variants or higher-grade families.

数据核验日期： 2026-09-05 ——数据由 XAIPART 元器件工程团队核验和整理

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