74HC165D,653 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
料号： 74HC165D,653 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.36 | $3.60 |
| 100 | $0.28 | $28.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
| 2,500 | $0.15 | $375.00 |
74HC165D,653 概述
A shift register is a sequential logic device that converts data between parallel and serial formats, used to expand the number of input or output pins available on a microcontroller. Within the broader taxonomy, a PISO shift register sits inside the shift register category, which is a subclass of sequential logic ICs, which itself belongs to the integrated circuit family and ultimately the semiconductor hypernym. The 74HC165 specifically enables one-directional parallel-to-serial conversion, complementing the 74HC595 (serial-to-parallel) to form a complete GPIO-expansion pair using only a few microcontroller pins.
Key features include a wide 2 V to 6 V supply range, ±5.2 mA output drive capability, 6 ns typical propagation delay at 5 V, and asynchronous parallel load control via the SH/LD pin. The clock-inhibit (CLK INH) function allows the user to freeze the shift state while continuing to clock the device, simplifying state-machine implementation. A serial data input (DS) permits cascading of multiple 74HC165 ICs to build arbitrarily wide input shift registers, and the complementary Q7 output provides a wired-OR option without external inversion.
Architecturally the part uses a high-speed Si-gate CMOS process that delivers LSTTL-equivalent drive strength at roughly an order of magnitude lower quiescent current. The internal design features eight master-slave flip-flops clocked by the rising edge of CP, with a parallel-load multiplexer controlled by the active-low SH/LD pin. When SH/LD is LOW, data on D0 through D7 is asynchronously loaded; when SH/LD is HIGH, the rising edge of CP shifts the register one position toward Q7. Power dissipation is dominated by dynamic switching losses and remains well below 1 mW quiescent at room temperature.
Typical applications include multi-input button-debounce and keypad scanning matrices, parallel sensor data acquisition over a single SPI/MCU pin, expanding microcontroller input count in industrial control panels, reading 7-segment multiplexed displays with limited GPIO, and shift-register multi-channel scanning for security keypads. Designers commonly cascade two or three 74HC165 ICs to read 16 or 24 inputs using only four microcontroller pins.
When designing with this part, place a 100 nF decoupling capacitor as close as possible to the VCC pin, keep the SH/LD and CP traces short to avoid ground-bounce-induced false clocking, and use a Schmitt-trigger buffer on the clock line if routing exceeds 50 mm. Note that the 74HCT variant is required when interfacing to 5 V TTL logic from a 3.3 V microcontroller.
This page synthesizes distributor pricing, drop-in alternatives from multiple manufacturers, application-specific design notes, and a parametric comparison not assembled in any single manufacturer datasheet, providing actionable information for both procurement and design engineering teams.
直接替换替代料： 74HC165D,653 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： 74HC165D,653 （相同外形与封装尺寸） ——差异在于 Logic Type, Output Type, Function, Operating Temperature, Package.
快速对比工具——选择替代料号进行并排对比：
74HC165D,652
✅ 直接替换✓ 有现货
$0.16 / 个
查看数据手册 →74HC165D-Q100,118
✅ 直接替换📋 参考替代料（不在目录中）
SN74HC165DR
✅ 直接替换📋 参考替代料（不在目录中）
SN74HC165NSR
✅ 直接替换📋 参考替代料（不在目录中）
74HC165D
✅ 直接替换✓ 有现货
$0.15 / 个
查看数据手册 →74HC165D,653 最大额定值与电气特性
| Logic Type | Shift Register (Parallel-in/Serial-out) |
| 功能 | Parallel or Serial to Serial |
| Number of Elements | 1 |
| Number of Bits per Element | 8 |
| 输出类型 | Differential (Q7 and Q7-bar complementary outputs) |
| Supply Voltage (VCC) | 2 V to 6 V |
| Input Voltage | 0 V to VCC |
| Output Drive (IO) | ±5.2 mA |
| 工作温度 | -40 C to +125 C |
| 封装 | 16-pin SOIC (SOT109-1) |
| 安装类型 | Surface Mount |
| MSL 等级 | 1 (per JEDEC J-STD-020) |
| RoHS 状态 | Compliant |
| JEDEC Compliance | JESD7A (per datasheet) |
| Pin Compatibility | LSTTL 74LS165 |
| Technology | High-speed Si-gate CMOS |
74HC165D,653 引脚配置
| 引脚 1 | SH/LD — Shift/Load control (active LOW: parallel load; HIGH: serial shift) |
| 引脚 2 | CLK — Clock input (rising edge shifts data toward Q7) |
| 引脚 3 | CLK INH — Clock inhibit (active HIGH: holds shift state) |
| 引脚 4 | D4 — Parallel data input bit 4 |
| 引脚 5 | D5 — Parallel data input bit 5 |
| 引脚 6 | D6 — Parallel data input bit 6 |
| 引脚 7 | D7 — Parallel data input bit 7 |
| 引脚 8 | GND — Ground (0 V) |
| 引脚 9 | Q7-bar — Complementary serial output (active LOW) |
| 引脚 10 | DS — Serial data input (for cascading multiple 74HC165 ICs) |
| 引脚 11 | D0 — Parallel data input bit 0 |
| 引脚 12 | D1 — Parallel data input bit 1 |
| 引脚 13 | D2 — Parallel data input bit 2 |
| 引脚 14 | D3 — Parallel data input bit 3 |
| 引脚 15 | CE — Clock enable (active LOW; alternate clock-inhibit input) |
| 引脚 16 | VCC — Positive supply (2 V to 6 V) |
典型应用
74HC165D,653 适用于 6 应用s: Button Matrix and Keypad Scanning, Industrial Control Panel Input Expansion, Parallel Sensor Data Acquisition, Multiplexed 7-Segment Display Reading, Security Keypad and Access Control Input, Microcontroller GPIO Expansion (Input Side).
Button Matrix and Keypad Scanning
The Nexperia 74HC165D,653 fits button-matrix scanning because it captures 8 parallel inputs asynchronously via the active-LOW SH/LD pin, then clocks them out serially over a single SPI-like MCU pin. With a typical tpd of 6 ns at 5 V and 2-6 V VCC tolerance, it can read a 16-key matrix using two cascaded 74HC165 ICs sharing SH/LD and CP lines, requiring only four microcontroller pins total. Compared with direct GPIO scanning, this approach frees MCU pins for other peripherals and provides hardware debounce-friendly synchronization via the parallel load strobe.
推荐
Industrial Control Panel Input Expansion
In industrial control panels with 16-64 limit switches, selector switches, or sensor contacts, the 74HC165D,653 enables reading all inputs through a 3-wire SPI interface to the PLC or MCU. Its -40 C to +125 C operating temperature range and JEDEC JESD7A compliance ensure reliable operation in factory environments. Cascading four 74HC165 ICs yields 32 inputs at update rates exceeding 1 MHz, while the ±5.2 mA drive and CMOS input thresholds provide excellent noise immunity against industrial EMI when paired with proper PCB layout and 100 nF VCC decoupling.
推荐
Parallel Sensor Data Acquisition
The 74HC165D,653 is well suited for acquiring data from multiple parallel-output sensors such as rotary encoders, parallel ADCs, or optocoupler arrays. By strobing SH/LD low then clocking out the 8-bit state, an MCU can sample up to 8 sensor channels per IC with deterministic timing. The complementary Q7 output allows direct cascading without external inversion, and the wide 2-6 V supply matches both 3.3 V and 5 V sensor banks. Designers should add a 100 nF decoupling capacitor adjacent to VCC and limit SH/LD pulse width to at least one CP period for reliable parallel-load timing.
推荐
Multiplexed 7-Segment Display Reading
When reading multiplexed 7-segment displays or LED bar graphs that share common anode/cathode lines, the 74HC165D,653 captures the 8-segment state per digit with minimal MCU pin overhead. Its 5.2 mA output drive can directly interface with low-current LED segment drivers, while the asynchronous parallel load enables snapshot sampling without flicker artifacts. The complementary Q7 output also simplifies timing analysis when verifying display refresh rates, and the SOIC-16 package fits standard 0.1-inch breadboard footprints for rapid prototyping.
推荐
Security Keypad and Access Control Input
For 12-key or 16-key security keypads, the 74HC165D,653 reduces MCU pin count from 8 to 3 (SH/LD, CP, Q7) while maintaining tamper-detection capability through synchronous parallel-load strobing. The HC family CMOS input thresholds provide excellent noise immunity against ESD events typical of human-touch interfaces, and the -40 C to +125 C range covers outdoor access-control installations. Two cascaded 74HC165 ICs read a full 4x4 matrix with hardware debounce support, with the CLK INH pin enabling scan freezing during keypad entry validation.
推荐
Microcontroller GPIO Expansion (Input Side)
The 74HC165D,653 is the input counterpart to the 74HC595 output-expander, together forming a complete GPIO-extension pair that communicates over a shared 3-wire SPI-like bus. Designers can read 16-64 inputs using only 4 MCU pins while preserving native GPIO for higher-speed peripherals. The 6 ns typical propagation delay at 5 V supports update rates above 50 MHz in burst mode, and the wide VCC range (2-6 V) enables direct connection to both 3.3 V and 5 V MCUs without level shifters. This makes the 74HC165D,653 ideal for legacy designs adding modern wireless or HMI features with limited GPIO budget.
推荐
推荐产品汇总
工程参考数据： 74HC165D,653 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 74HC165D,652 | 74HC165D-Q100,118 | SN74HC165DR | SN74HC165NSR | 74HC165D |
|---|---|---|---|---|---|---|
| Package | 16-SOIC (SOT109-1) | 16-SOIC (SOT109-1) - same | 16-SOIC (SOT109-1) - same | 16-SOIC - same | 16-SO - same | 16-SOIC (SOT109-1) - same |
| Brand | Nexperia | Nexperia | Nexperia | Texas Instruments | Texas Instruments | Nexperia |
| Supply Voltage | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V |
| Output Drive (IO) | ±5.2 mA | ±5.2 mA | ±5.2 mA | ±5.2 mA | ±5.2 mA | ±5.2 mA |
| Automotive Grade (AEC-Q100) | No | No | Yes (AEC-Q100) | No | No (industrial) | No |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C (AEC-Q100) | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C |
| Function | 8-bit PISO shift register | 8-bit PISO shift register | 8-bit PISO shift register | 8-bit PISO shift register | 8-bit PISO shift register | 8-bit PISO shift register |
| JEDEC Compliance | JESD7A | JESD7A | JESD7A + AEC-Q100 | JESD7A | JESD7A | JESD7A |
| Packaging Format | Tape & Reel | Tube | Tape & Reel | Tape & Reel | Tape & Reel | Bulk / Tube |
关键差异点
- Wide 2 V to 6 V supply range enables direct 3.3 V and 5 V system compatibility （对比 74LS165 (legacy LSTTL))
- Complementary Q7 and Q7-bar outputs eliminate external inverter for cascading （对比 SN74HC165DR (single-ended Q7 only on certain variants))
- Asynchronous parallel load decouples capture timing from clock domain （对比 Synchronous-only shift registers)
- Clock-inhibit (CLK INH) function freezes shift state while continuing to clock （对比 Basic shift registers without inhibit)
设计说明
Place a 100 nF ceramic decoupling capacitor as close as possible to the VCC pin (pin 16) and route it directly to the GND pin (pin 8) with the shortest possible trace. Add a 10 uF bulk capacitor on the PCB power rail near the 74HC165D,653 if multiple high-speed CMOS ICs share the same VCC. The 74HC family typically draws less than 1 mW quiescent at room temperature, but dynamic switching currents during CP edges require local decoupling to prevent VCC droop-induced false clocking. According to Nexperia application guidance, decoupling is mandatory for reliable operation above 1 MHz clock rates.
Keep the SH/LD and CP traces short (under 50 mm recommended) and route them away from high-current switching lines such as relay coils or motor phases. Place a ground guard trace between parallel data inputs (D0-D7) and any noisy analog signals to reduce crosstalk. The exposed copper pad beneath the SOIC package should be soldered to a grounded copper pour for thermal dissipation and improved EMI performance; the SOIC-16 thermal resistance is approximately 90 C/W and benefits significantly from even 100 mm^2 of copper area on a 1 oz PCB.
When cascading multiple 74HC165 ICs, connect each stage's Q7 output to the next stage's DS input with a short trace, and provide a 100 nF decoupling capacitor at each stage's VCC pin. If the SH/LD trace exceeds 50 mm or routes near noisy signals, add a 74HC14 Schmitt-trigger buffer between the MCU and the SH/LD pin to prevent false parallel-load strobes caused by ground bounce. The complementary Q7-bar output can be left floating if unused, but should not be tied to VCC or GND; according to the Nexperia datasheet, leaving CMOS outputs floating is acceptable when not connected.
Do not confuse the HC and HCT variants: 74HC has CMOS input thresholds (VIH ≈ 0.7×VCC) while 74HCT has TTL input thresholds (VIH = 2.0 V). Mixing HC and HCT in 5 V systems can cause intermittent logic failures when input edges are slow. Do not apply inputs before VCC is stable; the absolute maximum rating of -0.5 V to VCC+0.5 V must be respected, and the parallel-load pulse width must exceed the datasheet-specified minimum (typically 20 ns) for reliable asynchronous capture. Never connect unused parallel inputs (D0-D7) floating - they will pick up noise and cause erratic shift-register behavior; tie them to either VCC or GND through a 10 kohm resistor.
合规信息
RoHS compliant per Nexperia product page. Not AEC-Q100 qualified - choose 74HC165D-Q100,118 for automotive. JEDEC JESD7A compliant per datasheet general description. LSTTL 74LS165 pin-compatible per datasheet.
