AD7651ACPZRL - 16-Bit 100kSPS PulSAR ADC | Analog Devices
料号： AD7651ACPZRL ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $17.12 | $171.20 |
| 100 | $15.55 | $1,555.00 |
| 500 | $14.2 | $7,100.00 |
| 1,000 | $12.95 | $12,950.00 |
| 2,500 | $11.8 | $29,500.00 |
AD7651ACPZRL 概述
A SAR ADC is a successive-approximation register analog-to-digital converter that uses a binary-search charge-redistribution architecture to resolve each conversion in N clock cycles for an N-bit result. The architecture delivers deterministic latency, low power dissipation, and excellent dynamic performance at moderate sample rates, making SAR converters the category of choice for multiplexed data acquisition, motor control, and industrial instrumentation where the converter sits within the broader signal chain of sensor -> signal conditioning -> ADC -> MCU/DSP -> communication.
Key features include ±15V input overvoltage protection on the analog inputs, on-chip 2.5V reference with low 5 ppm/°C typical temperature drift, 84 dB SNR at 10 kHz input, and selectable bipolar (±5V, ±10V) or unipolar (0-2.5V, 0-5V, 0-10V) input ranges via hardware pin strapping. The LFCSP-48 7x7 footprint provides a thermal pad that lowers junction-to-PCB thermal resistance and supports the ±10V true-bipolar input configuration directly from ±15V rails without external protection.
Typical applications include industrial process control (PLC analog input modules), power-line monitoring, multi-axis motor control current sensing, and portable instrumentation. The AD7651ACPZRL's combination of bipolar input range, on-chip reference, and parallel interface simplifies board layout compared to discrete ADC + external reference + amplifier signal chains. When designing with this part, observe the recommended 10uF + 0.1uF decoupling network on each supply pin and route the analog and digital ground planes as a single star-grounded split to preserve 84 dB SNR.
直接替换替代料： AD7651ACPZRL ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD7651ACPZRL （相同外形与封装尺寸） ——差异在于 Package, Input Type, Architecture, Operating Temperature, Resolution.
快速对比工具——选择替代料号进行并排对比：
AD7650ACPZRL
✅ 直接替换✓ 有现货
$17.92 / 个
查看数据手册 →AD7641BCPZRL
✅ 直接替换✓ 有现货
$19.8 / 个
查看数据手册 →AD7623ACPZRL
✅ 直接替换✓ 有现货
$20.8 / 个
查看数据手册 →AD7651ACPZRL 最大额定值与电气特性
| 分辨率 | 16 bit |
| Sample Rate | 100 kSPS |
| Number of Channels | 1 |
| Architecture | SAR (Successive Approximation Register) |
| Input Type | Pseudo-Bipolar / Unipolar, single-ended |
| Unipolar Input Range | 0 V to 2.5 V (true), 0-5V/0-10V software-selectable |
| Bipolar Input Range | ±5 V, ±10 V |
| Analog Supply Voltage (AVCC) | 5 V |
| Digital Supply Voltage (DVDD) | 2.7 V to 5.25 V |
| Input Overvoltage Protection | ±15 V |
| On-Chip Reference | 2.5 V internal |
| SNR | 84 dB at 10 kHz input |
| 接口 | Parallel / Serial 16-bit |
| 封装 | 48-LFCSP-VQ (7x7 mm), MO-220-VKKD-2 |
| 工作温度 | -40 C to +85 C |
| Screening Level | Industrial |
| RoHS 状态 | Compliant |
AD7651ACPZRL 引脚配置
| 引脚 1 | DGND — Digital ground |
| 引脚 2 | AVDD — 5V analog supply |
| 引脚 3 | AVDD — 5V analog supply |
| 引脚 4 | AVDD — 5V analog supply |
| 引脚 5 | AGND — Analog ground |
| 引脚 6 | REF — 2.5V reference input/output |
| 引脚 7 | REFGND — Reference ground |
| 引脚 8 | IN+ — Positive analog input |
| 引脚 9 | IN- — Negative analog input |
| 引脚 10 | AGND — Analog ground |
| 引脚 11 | REGCAP — Internal regulator bypass capacitor |
| 引脚 12 | AGND — Analog ground |
| 引脚 13 | DVDD — Digital supply (2.7V-5.25V) |
| 引脚 14 | DGND — Digital ground |
| 引脚 15 | RD — Read input (parallel mode) |
| 引脚 16 | CS — Chip select (active low) |
| 引脚 17 | BUSY — Busy output (active high) |
| 引脚 18 | CNVST — Conversion start input |
| 引脚 19 | D15 — Data bit 15 (MSB) |
| 引脚 20 | D14 — Data bit 14 |
| 引脚 21 | D13 — Data bit 13 |
| 引脚 22 | D12 — Data bit 12 |
| 引脚 23 | D11 — Data bit 11 |
| 引脚 24 | D10 — Data bit 10 |
| 引脚 25 | D9 — Data bit 9 |
| 引脚 26 | D8 — Data bit 8 |
| 引脚 27 | D6 — Data bit 6 |
| 引脚 28 | D5 — Data bit 5 |
| 引脚 29 | D4 — Data bit 4 |
| 引脚 30 | D3 — Data bit 3 |
| 引脚 31 | D2 — Data bit 2 |
| 引脚 32 | D1 — Data bit 1 |
| 引脚 33 | D0 — Data bit 0 (LSB) |
| 引脚 34 | D7 — Data bit 7 (byte-mode) |
| 引脚 35 | OB/2 |
| 引脚 36 | RANGE — Input range select |
| 引脚 37 | HW/SW — Hardware/software mode select |
| 引脚 38 | IMPULSE — Impulse mode select |
| 引脚 39 | DGND — Digital ground |
| 引脚 40 | DGND — Digital ground |
| 引脚 41 | SDOUT — Serial data output |
| 引脚 42 | SCLK — Serial clock |
| 引脚 43 | SYNC — Synchronization input |
| 引脚 44 | RESET — Reset input (active low) |
| 引脚 45 | STBY — Standby mode input |
| 引脚 46 | AGND — Analog ground |
| 引脚 47 | AVDD — 5V analog supply |
| 引脚 48 | AVDD — 5V analog supply |
典型应用
AD7651ACPZRL 适用于 6 应用s: Industrial PLC Analog Input Module, Power-Line Voltage & Current Monitoring, Multi-Axis Motor Control Current Sensing, Portable Battery-Powered Instrumentation, Medical Patient Monitoring, Data Acquisition Systems.
Industrial PLC Analog Input Module
The AD7651ACPZRL is a benchmark part for industrial PLC analog input modules that digitize ±10V or 0-10V field signals. Its ±15V input overvoltage protection tolerates mis-wiring and field transients that would destroy lower-overvoltage ADCs, while the integrated 2.5V reference eliminates an external reference IC and reduces BOM cost. At 100 kSPS it oversamples typical 4-20 mA / ±10V scan loops many times over, allowing digital averaging to push ENOB beyond 14 bits. Used in tandem with an ARM Cortex-M4 MCU for IEC 61131-3 control loops.
推荐
Power-Line Voltage & Current Monitoring
In power-line monitoring systems the AD7651ACPZRL simultaneously digitizes mains voltage and current at 100 kSPS, capturing enough harmonic bandwidth for IEC 61000-4-7 harmonic analysis up to the 50th harmonic. Its pseudo-bipolar input directly interfaces to ±10V current-transformer / voltage-divider signal conditioning, and the parallel interface streams conversion results into an FPGA or DSP without buffering latency. Hardware-configurable input range lets one design cover both 110V and 240V nominal mains systems.
推荐
Multi-Axis Motor Control Current Sensing
The AD7651ACPZRL is well suited to multi-axis servo-drive current sensing loops. Three ADCs sample phase currents synchronously at 100 kSPS with deterministic SAR latency, enabling field-oriented control (FOC) with sub-microsecond loop delay. The integrated reference holds gain stability across the 0-85°C industrial range, and the parallel interface feeds direct conversion data into a DSP without handshaking overhead. Optional ±15V OVP protects against motor back-EMF transients during braking events.
推荐
Portable Battery-Powered Instrumentation
In portable instrumentation the AD7651ACPZRL's 5V single-supply operation and SAR architecture deliver 16-bit performance at milliwatt power levels - the device typically dissipates 10-15 mW at 100 kSPS, an order of magnitude below continuous-sampling delta-sigma ADCs. The integrated 2.5V reference eliminates a separate reference IC and its quiescent current. Power-down modes between conversions extend battery life in handheld data-logger applications where the ADC is sampled periodically rather than continuously.
推荐
Medical Patient Monitoring
For medical patient-monitoring front ends the AD7651ACPZRL provides 16-bit, 100 kSPS digitization of ECG, SpO2, and temperature sensor channels. Its ±15V input overvoltage tolerance protects against defibrillator discharge transients that are common in clinical environments. The integrated reference ensures long-term gain stability across patient-monitoring calibration cycles, and the parallel interface streams data directly into a safety-certified MCU. The exposed-pad LFCSP-48 footprint supports compact 4-layer PCB layouts.
推荐
Data Acquisition Systems
The AD7651ACPZRL is a foundational building block for parallel multi-channel data-acquisition (DAQ) boards. Multiple ADCs can be synchronized through a shared CNVST signal so that all channels sample within nanoseconds of each other - critical for vibration, acoustic, and transient-recording applications. At 100 kSPS the ADC handles 16 simultaneous channels at 6.25 kSPS each in round-robin scan, or one channel at full throughput for single-channel transient capture.
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推荐产品汇总
工程参考数据： AD7651ACPZRL ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD7650ACPZRL | AD7641BCPZRL | AD7623ACPZRL | AD7623ASTZRL | AD7264BSTZ-5-RL7 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-LFCSP-VQ (7x7) | 48-LFCSP-VQ (7x7) - same | 48-LFCSP (different footprint detail) | 48-LFCSP-VQ (7x7) - same | 48-LQFP (7x7) - different | 48-LQFP (7x7) - different |
| Resolution | 16 bit | 16 bit | 18 bit | 16 bit | 16 bit | 14 bit |
| Sample Rate | 100 kSPS | 100 kSPS | 2 MSPS | 1.2 MSPS | 1.2 MSPS | 1 MSPS (dual) |
| On-Chip Reference | Yes (2.5V) | No (external) | No (external) | No (external) | No (external) | Yes |
| Input Range | ±10V bipolar / 0-10V unipolar, ±15V OVP | ±10V bipolar, ±15V OVP | Differential ±VREF | Differential ±VREF | Differential ±VREF | ±10V bipolar (dual) |
| Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Interface | Parallel / Serial | Parallel / Serial | Parallel / Serial | Parallel / Serial | Parallel / Serial | Parallel / Serial |
关键差异点
- Integrated 2.5V reference eliminates external reference IC （对比 AD7650ACPZRL)
- ±15V input overvoltage protection tolerates field transients （对比 AD7264BSTZ-5-RL7)
- 100 kSPS throughput at 16-bit single-channel resolution （对比 AD7623ACPZRL)
设计说明
Estimated: the AD7651ACPZRL draws approximately 15 mW at 100 kSPS from a 5V analog supply, plus 5 mW from the digital supply. Place a 10uF tantalum + 0.1uF ceramic decoupling pair within 5 mm of each AVDD pin (48-LFCSP-VQ pins 2-4, 47-48) and within 5 mm of the DVDD pin (pin 13). The REGCAP pin (pin 11) requires a 1uF ceramic bypass to AGND to stabilize the internal core regulator. Inadequate REGCAP bypassing is the most common cause of elevated noise and reduced SNR in field returns.
Use a 4-layer PCB with a dedicated ground plane on layer 2 directly under the AD7651ACPZRL. Star-ground the analog and digital grounds at the exposed pad (EP) only - do not allow digital return currents to flow under the analog input traces. Keep the IN+/IN- traces as short as possible (under 10 mm) and route them as a tightly-coupled differential pair on the top layer above a continuous ground pour. Per the datasheet, the 84 dB SNR cannot be achieved without this layout discipline.
Do not load the internal reference (pin 6 REF) with more than 1 mA DC - this perturbs reference voltage and degrades gain accuracy. If the design requires driving multiple ADC references from one AD7651, buffer the REF pin with an AD8021 or OPA627. Also avoid leaving the BUSY pin (pin 17) floating; pull it through 10k to DVDD if not actively monitored - a floating BUSY pin can inject coupling into adjacent analog pins on some production lots.
Estimated: when sampling at 100 kSPS, the analog input bandwidth must support the input step transient at the start of acquisition. Per datasheet the ADC has 25 ns acquisition time, requiring the front-end op-amp to settle to 16-bit accuracy (< 1 LSB = 153uV at ±10V range) within that window. A bandwidth of at least 5 MHz and slew rate of 20 V/us are minimum; the AD8021 or ADA4627 are recommended buffers for the TC decoupling.
合规信息
RoHS and lead-free confirmed per Analog Devices product page. Halogen-free status not explicitly listed in verified data - confirm with manufacturer. Not AEC-Q100 qualified (industrial-grade part).
