AD9057BRS-60 - 8-Bit 60MSPS ADC | Analog Devices
料号： AD9057BRS-60 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $11.42 | $11.42 |
| 10 | $10.27 | $102.70 |
| 100 | $8.85 | $885.00 |
| 500 | $7.42 | $3,710.00 |
| 1,000 | $6.18 | $6,180.00 |
AD9057BRS-60 概述
An 8-bit ADC is a converter that quantizes an analog input signal into 256 discrete digital codes (2^8) at a specified sample rate. In the broader taxonomy, the AD9057 belongs to flash / pipelined ADCs (sub-category of data converters), which sit inside signal-chain ICs and ultimately under analog/mixed-signal ICs. ADCs of this class are typically used as the front-end digitizer between a sensor or analog conditioning stage and a digital ASIC, FPGA, or DSP that performs further processing.
Key features of the AD9057BRS-60 include 200 mW typical power dissipation at full sample rate, a 10 mW power-down mode for portable/battery applications, an on-chip 2.5 V reference that eliminates an external reference IC, 1 V p-p analog input range, single +5 V analog supply operation, and 3 V logic interface compatibility. The 120 MHz analog input bandwidth comfortably exceeds the 60 MSPS Nyquist requirement, allowing gentle anti-alias filter design and supporting undersampling IF architectures. The integrated track-and-hold minimizes aperture jitter and sample-rate-dependent phase error.
Architecturally, the AD9057 is implemented as an 8-bit flash ADC with a front-end sample-and-hold and on-chip reference. The flash architecture gives single-cycle latency (one clock of pipeline delay is sometimes quoted for the pipelined grade) and excellent dynamic performance for repetitive or single-shot digitizations. Encoding logic is TTL/CMOS-compatible, allowing direct connection to a 5 V-tolerant FPGA or 3.3 V logic without level shifters in most cases.
Typical applications include digital oscilloscopes, professional video digitizers, CCD/camera signal processing, medical ultrasound receive paths, cable modem upstream/downstream QAM demodulators, and general-purpose data-acquisition front ends. The 60 MSPS grade is the balanced middle option of the family: it provides more headroom than 40 MSPS for wide-bandwidth signals while consuming less power than the 80 MSPS grade.
Design tip: keep the analog input trace impedance-controlled (typically 50 ohm or 75 ohm) and place a termination resistor at the ADC input pin to damp the track-and-hold kick-back; add small RC anti-alias filtering ahead of the input. Decouple VDD with 0.1 uF and 10 uF ceramic capacitors placed within 5 mm of the supply pins.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes that go beyond what the manufacturer datasheet provides alone.
直接替换替代料： AD9057BRS-60 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AD9057BRS-40
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRS-80
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRSZ-60
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRSZ-80
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRSZ-RL40
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRS-RL60
✅ 直接替换📋 参考替代料（不在目录中）
AD9057BRS-60 最大额定值与电气特性
| 分辨率 | 8 bit |
| Sample Rate (Encode Rate) | 60 MSPS |
| Architecture | Flash / Pipelined |
| Analog Input Bandwidth (Full Power) | 120 MHz |
| Analog Input Range | 1 V p-p |
| Number of Input Channels | 1 |
| 电源电压 | +5 V single supply |
| Logic Interface | 3 V / 5 V CMOS/TTL |
| Power Dissipation (Typ) | 200 mW at 60 MSPS |
| Power-Down Mode Power | 10 mW |
| Internal Reference | +2.5 V on-chip |
| Track-and-Hold | On-chip |
| 工作温度范围 | -40 C to +85 C |
| 封装 | 20-pin SSOP (RS-20) |
| 安装类型 | Surface Mount |
AD9057BRS-60 引脚配置
| 引脚 1 | AVDD — +5 V analog supply |
| 引脚 2 | AVDD — +5 V analog supply |
| 引脚 3 | REF — Internal +2.5 V reference (decouple to ground) |
| 引脚 4 | AIN — Analog input |
| 引脚 5 | AGND — Analog ground |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | CLK — Encode clock input |
| 引脚 8 | PWRDN — Power-down control (active high) |
| 引脚 9 | D7 — Data output bit 7 (MSB) |
| 引脚 10 | D6 — Data output bit 6 |
| 引脚 11 | D5 — Data output bit 5 |
| 引脚 12 | D4 — Data output bit 4 |
| 引脚 13 | DGND — Digital ground |
| 引脚 14 | D3 — Data output bit 3 |
| 引脚 15 | D2 — Data output bit 2 |
| 引脚 16 | D1 — Data output bit 1 |
| 引脚 17 | D0 — Data output bit 0 (LSB) |
| 引脚 18 | DRVDD — Digital output driver supply (3 V or 5 V) |
| 引脚 19 | DRVDD — Digital output driver supply (3 V or 5 V) |
| 引脚 20 | DGND — Digital ground |
典型应用
AD9057BRS-60 适用于 6 应用s: Digital Oscilloscope Front End, Video Digitizer / Broadcast Equipment, Cable Modem / QAM IF Sampling, CCD / Camera Image Sensor Digitizer, Ultrasound Receive Path, General Data Acquisition Front End.
Digital Oscilloscope Front End
The AD9057BRS-60 is well suited as the input-stage digitizer in entry-level and mid-range digital storage oscilloscopes. Its 60 MSPS encode rate captures single-shot bandwidths well beyond 30 MHz while the 120 MHz analog input bandwidth flattens the frequency response well past Nyquist, letting designers use a simpler anti-alias filter than a brick-wall design would require. The 1 V p-p analog input range and integrated track-and-hold simplify the front-end analog conditioning, and the 200 mW typical dissipation keeps thermal density manageable in multi-channel scope mainboards. The single +5 V supply and 3 V / 5 V CMOS outputs allow direct connection to a 3.3 V FPGA capture buffer without level shifters.
推荐
Video Digitizer / Broadcast Equipment
Broadcast video digitizers benefit from the AD9057BRS-60's 60 MSPS encode rate, which exceeds the 27 MSPS required for 4:2:2 SDTV sampling and the 54 MSPS needed for many HD component formats. The 120 MHz analog input bandwidth provides flat response across the full video spectrum, minimizing group-delay distortion that would otherwise cause chroma phase errors. The internal +2.5 V reference keeps DC accuracy stable across temperature without an external reference IC, and the 20-pin SSOP package enables compact multi-channel digitizer cards. The 10 mW power-down mode supports standby operation in broadcast equipment where regulatory idle-power targets apply.
推荐
Cable Modem / QAM IF Sampling
Cable modem upstream and downstream paths use the AD9057BRS-60 as an IF-sampling ADC. The 60 MSPS sample rate supports DOCSIS downstream channel plans centered near 40-44 MHz IF, while the 120 MHz analog bandwidth accommodates undersampling of higher IF frequencies commonly found in head-end equipment. The flash architecture delivers single-cycle latency, which simplifies timing recovery in the demodulator DSP. The on-chip +2.5 V reference provides the low-drift threshold that QAM constellations require for low bit-error-rate performance, and the 200 mW dissipation keeps multi-channel CMTS line cards within their thermal envelope.
推荐
CCD / Camera Image Sensor Digitizer
Industrial and machine-vision cameras using linear or area CCD sensors use the AD9057BRS-60 to digitize the analog video output from the sensor's correlated double-sampling stage. The 60 MSPS encode rate handles 60 fps progressive-scan megapixel sensors where each line must be sampled at high rate. The integrated track-and-hold is critical here, because CCD output amplifiers cannot drive a switched-capacitor ADC input directly without sample-rate-dependent droop. The single +5 V supply simplifies the camera head's power tree, and the 20-pin SSOP package fits inside compact camera modules with tight Z-height constraints.
推荐
Ultrasound Receive Path
Medical ultrasound receivers digitize the post-TGC, post-beamformed RF signal at sample rates from 40 to 80 MSPS with 8-bit resolution - exactly the niche the AD9057BRS-60 targets. The 120 MHz analog bandwidth captures harmonic imaging frequencies above the fundamental 5 MHz transmit band, while the 60 MSPS encode rate provides sufficient oversampling for digital demodulation to baseband I/Q in the FPGA. Low aperture uncertainty from the integrated track-and-hold is essential for preserving phase coherence across receive channels. The 200 mW typical dissipation is acceptable for 32- to 64-channel portable ultrasound carts where per-channel thermal budget is tight.
推荐
General Data Acquisition Front End
Bench-top and rack-mount data acquisition systems use the AD9057BRS-60 as a high-sample-rate, moderate-resolution digitizer for vibration analysis, sonar, and instrumentation front ends. The 60 MSPS rate captures signals up to 25 MHz without aliasing, while the 8-bit resolution suits envelope-detection and trigger-threshold applications where dynamic range requirements are moderate. The single +5 V supply simplifies backplane power design in VXI/PXI/LXI chassis, and the SSOP-20 package is well supported by standard automated assembly lines. The on-chip reference and power-down mode give portable DAQ modules low standby drain between acquisition bursts.
推荐
推荐产品汇总
工程参考数据： AD9057BRS-60 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD9057BRS-40 | AD9057BRS-80 | AD9057BRSZ-60 | AD9057BRSZ-80 | AD9057BRSZ-RL40 | AD9057BRS-RL60 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 20-pin SSOP (RS-20) | 20-pin SSOP - same | 20-pin SSOP - same | 20-pin SSOP - same | 20-pin SSOP - same | 20-pin SSOP - same | 20-pin SSOP - same |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit |
| Sample Rate (MSPS) | 60 | 40 | 80 | 60 | 80 | 40 | 60 |
| Analog Input Bandwidth | 120 MHz | 120 MHz | 120 MHz | 120 MHz | 120 MHz | 120 MHz | 120 MHz |
| Power Dissipation (Typ) | 200 mW | 200 mW (lower at 40 MSPS) | 200 mW (higher at 80 MSPS) | 200 mW | 200 mW | 200 mW (lower at 40 MSPS) | 200 mW |
| Supply Voltage | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single |
| Internal Reference | +2.5 V | +2.5 V | +2.5 V | +2.5 V | +2.5 V | +2.5 V | +2.5 V |
| Packaging Form | Tube (BRS) | Tube | Tube | Tube (Z = RoHS) | Tube (Z = RoHS) | Tape & Reel (RL = T&R) | Tape & Reel (RL = T&R) |
关键差异点
- Highest sample rate of the BRS-60 grade at 60 MSPS, balancing speed and power （对比 AD9057BRS-40)
- Lower power and lower cost than the 80 MSPS speed grade （对比 AD9057BRS-80)
- RoHS-compliant version available in identical SSOP-20 footprint （对比 AD9057BRSZ-60)
设计说明
Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each AVDD and DRVDD pin, and add a 10 uF tantalum or ceramic bulk capacitor on each supply rail. The internal +2.5 V reference also requires a 0.1 uF ceramic decoupling capacitor at the REF pin to ground; inadequate REF decoupling is the most common cause of degraded SFDR in flash ADCs.
Drive the analog input with a source impedance of 50 ohm or 75 ohm and place a matching termination resistor physically close to the AIN pin to damp the track-and-hold kick-back. Use a small RC (typically 10 ohm + 33 pF) anti-alias network ahead of the input; the 120 MHz analog bandwidth lets you use a gentle filter order rather than a steep brick-wall design.
Do not confuse the BRS-40 / BRS-60 / BRS-80 speed-grade suffixes - all three share the same SSOP-20 footprint and pinout but encode rate and AC specs differ. For new designs where RoHS compliance is required, order the BRSZ-40 / BRSZ-60 / BRSZ-80 variants; the bare BRS suffix is non-RoHS. Avoid driving the encode clock (CLK) with a long trace - use a series 33 ohm damping resistor at the clock driver output.
The 200 mW typical dissipation at 60 MSPS is concentrated in a small SSOP-20 die; provide a continuous ground plane under the package and stitch AVDD / DRVDD returns together at one point near the ADC to avoid digital return currents contaminating the analog ground. Use the PWRDN pin to drop dissipation to 10 mW during idle periods in battery-powered or standby applications.
合规信息
The bare BRS-60 (without Z suffix) is non-RoHS per Analog Devices naming convention; the BRSZ-60 variant is RoHS-compliant. AEC-Q100 qualification status not stated in provided data; this part is intended for industrial / commercial / medical imaging rather than automotive.
