AD9238BSTZ-40 - Dual 12-Bit 40 MSPS ADC 64-LQFP | Analog Devices
料号： AD9238BSTZ-40 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.75 | $287.50 |
| 100 | $23.4 | $2,340.00 |
| 500 | $19.95 | $9,975.00 |
| 1,000 | $17.2 | $17,200.00 |
AD9238BSTZ-40 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts real-world analog signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Within the broader signal chain taxonomy, the AD9238 belongs to the data-converter family, specifically the high-speed pipelined ADC sub-family, which sits between successive-approximation register (SAR) ADCs (lower speed, higher precision) and flash ADCs (highest speed, lower resolution). Pipelined ADCs balance speed and resolution, making them the dominant choice for communications, medical imaging, and industrial instrumentation in the 10 to 250 MSPS range.
Key specifications include a 70 dB SNR at 9.7 MHz input (per the AD9238 datasheet), 2 V p-p differential input range, and programmable on-chip input bias modes for AC-coupled or DC-coupled signal chains. The device offers flexible digital output formatting - straight binary, twos complement, and gray code - with LVDS-compatible or CMOS output options. A built-in duty-cycle stabilizer (DCS) compensates for clock duty-cycle distortion, preserving SNR across realistic clock sources.
The AD9238 uses a multi-stage pipelined architecture with digital error correction. Each stage quantizes a coarse residue, amplified and passed to the next stage, enabling high throughput with moderate hardware cost. The integrated reference and sample-and-hold amplifiers allow compact PCB designs, especially in multi-channel systems where two matched converters share a common clock and reference.
Typical applications include IF signal digitization in communications receivers, multi-channel data acquisition, medical ultrasound beamformers, and portable instrumentation. It is also widely used in radar processing and I/Q demodulation paths in software-defined radio.
Designers should note that the AD9238BSTZ-40 is pin-compatible with the AD9248 (14-bit) and is offered in speed grades of 20 MSPS, 40 MSPS, and 65 MSPS, allowing a single PCB layout to support multiple performance tiers. Use a low-jitter clock and short, impedance-controlled analog input traces to realize the datasheet's SNR performance.
This page synthesizes distributor pricing, drop-in alternatives (same-PCB variants and ADI speed-grade equivalents), and practical design notes not consolidated in the manufacturer datasheet.
直接替换替代料： AD9238BSTZ-40 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD9238BSTZ-40 （相同外形与封装尺寸） ——差异在于 Number of Channels, Package, Resolution, Operating Temperature, Reference.
快速对比工具——选择替代料号进行并排对比：
AD9238BSTZ-65
✅ 直接替换📋 参考替代料（不在目录中）
AD9238BSTZ-20
✅ 直接替换📋 参考替代料（不在目录中）
AD9238BSTRL-40
✅ 直接替换✓ 有现货
$20.4 / 个
查看数据手册 →AD9248BSTZ-40
✅ 直接替换📋 参考替代料（不在目录中）
AD9248BSTZ-65
✅ 直接替换📋 参考替代料（不在目录中）
AD9238BST-65
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD9238BSTZ-40 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual) |
| 采样率 | 40 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| 输入电压范围 | 1 V p-p to 2 V p-p differential (programmable) |
| 电源电压 | 2.7 V to 3.6 V (single 3.3 V typical) |
| Power Consumption | 330 mW at 40 MSPS |
| SNR | 70 dBFS at 9.7 MHz input |
| Reference | Internal (integrated) |
| Digital Output Format | CMOS / LVDS compatible; straight binary or twos complement |
| 工作温度 | -40C to +85C (industrial) |
| 封装 | 64-LQFP (7 mm x 7 mm) |
| 安装类型 | Surface Mount |
| MSL 等级 | 3 (168 hours) |
| RoHS 状态 | Compliant |
AD9238BSTZ-40 引脚配置
| 引脚 1 | DRVDD — Digital output driver supply (3.3V) |
| 引脚 2 | DGB1A — Digital ground - Channel A outputs |
| 引脚 3 | D0A — Channel A digital output bit 0 (LSB) |
| 引脚 4 | D1A — Channel A digital output bit 1 |
| 引脚 5 | D2A — Channel A digital output bit 2 |
| 引脚 6 | D3A — Channel A digital output bit 3 |
| 引脚 7 | D4A — Channel A digital output bit 4 |
| 引脚 8 | D5A — Channel A digital output bit 5 |
| 引脚 9 | D6A — Channel A digital output bit 6 |
| 引脚 10 | D7A — Channel A digital output bit 7 |
| 引脚 11 | D8A — Channel A digital output bit 8 |
| 引脚 12 | D9A — Channel A digital output bit 9 |
| 引脚 13 | D10A — Channel A digital output bit 10 |
| 引脚 14 | D11A — Channel A digital output bit 11 (MSB) |
| 引脚 15 | DRA — Data ready output, Channel A |
| 引脚 16 | DRVDD — Digital output driver supply |
| 引脚 17 | DFS — Data format select |
| 引脚 18 | DCS_EN — Duty cycle stabilizer enable |
| 引脚 19 | OGND — Output driver ground |
| 引脚 20 | DRVDD — Digital output driver supply |
| 引脚 21 | OGND — Output driver ground |
| 引脚 22 | DRVDD — Digital output driver supply |
| 引脚 23 | DFS — Data format select input |
| 引脚 24 | DGB1B — Digital ground - Channel B outputs |
| 引脚 25 | D0B — Channel B digital output bit 0 (LSB) |
| 引脚 26 | D1B — Channel B digital output bit 1 |
| 引脚 27 | D2B — Channel B digital output bit 2 |
| 引脚 28 | D3B — Channel B digital output bit 3 |
| 引脚 29 | D4B — Channel B digital output bit 4 |
| 引脚 30 | D5B — Channel B digital output bit 5 |
| 引脚 31 | D6B — Channel B digital output bit 6 |
| 引脚 32 | D7B — Channel B digital output bit 7 |
| 引脚 33 | D8B — Channel B digital output bit 8 |
| 引脚 34 | D9B — Channel B digital output bit 9 |
| 引脚 35 | D10B — Channel B digital output bit 10 |
| 引脚 36 | D11B — Channel B digital output bit 11 (MSB) |
| 引脚 37 | DRB — Data ready output, Channel B |
| 引脚 38 | OGND — Output driver ground |
| 引脚 39 | DRVDD — Digital output driver supply |
| 引脚 40 | MUX_SELECT — Channel multiplexing select input |
| 引脚 41 | SENSE — Reference / mode sense input |
| 引脚 42 | REFTS — Reference decoupling - top |
| 引脚 43 | REFBS — Reference decoupling - bottom |
| 引脚 44 | REGCOMD — Common voltage decoupling |
| 引脚 45 | REGFMD — Full-scale voltage decoupling |
| 引脚 46 | VREF — Voltage reference input/output |
| 引脚 47 | AGNDB — Analog ground - Channel B |
| 引脚 48 | AINB- — Channel B analog input - negative |
| 引脚 49 | AINB+ — Channel B analog input - positive |
| 引脚 50 | AGNDB — Analog ground - Channel B |
| 引脚 51 | AGND — Analog ground |
| 引脚 52 | CLKB- — Channel B clock input - negative |
| 引脚 53 | CLKB+ — Channel B clock input - positive |
| 引脚 54 | AGND — Analog ground |
| 引脚 55 | AVDD — Analog supply (3.3V) |
| 引脚 56 | CLKA+ — Channel A clock input - positive |
| 引脚 57 | CLKA- — Channel A clock input - negative |
| 引脚 58 | AVDD — Analog supply (3.3V) |
| 引脚 59 | AGNDA — Analog ground - Channel A |
| 引脚 60 | AINA+ — Channel A analog input - positive |
| 引脚 61 | AINA- — Channel A analog input - negative |
| 引脚 62 | AGNDA — Analog ground - Channel A |
| 引脚 63 | REGA — Channel A reference/decoupling |
| 引脚 64 | REFD — Reference decoupling pin |
典型应用
AD9238BSTZ-40 适用于 7 应用s: Communications IF Digitization, Medical Ultrasound Beamforming, Multi-Channel Data Acquisition, Portable Instrumentation, Radar and Lidar Signal Processing, Software-Defined Radio (SDR) Baseband, Touchscreen and Image-Sensor Front-End.
Communications IF Digitization
The AD9238BSTZ-40's dual channels and 40 MSPS throughput suit intermediate-frequency (IF) digitization in software-defined and diversity receivers. Each channel handles an independent I or Q path with the 2 V p-p differential input range accepting the post-mixer output directly. The on-chip duty-cycle stabilizer tolerates real-world clock jitter, preserving the 70 dB SNR across the cellular, land-mobile, and point-to-point radio bands that engineers target at this sample rate.
推荐
Medical Ultrasound Beamforming
In multi-channel ultrasound systems, the AD9238BSTZ-40's dual-channel integration halves board space per channel compared with single-channel ADCs, and the 40 MSPS rate matches typical 5 to 20 MHz transducer bandwidth. The integrated sample-and-hold amplifier allows simultaneous sampling on both channels, essential for phase-coherent beamforming across an array. Low input-referred noise preserves diagnostic resolution in B-mode and Doppler imaging applications.
推荐
Multi-Channel Data Acquisition
Industrial data-acquisition cards use the AD9238BSTZ-40's two channels to capture simultaneous bipolar signals from sensors like accelerometers, strain gauges, or photodiodes. The differential input rejects common-mode noise picked up on long cables from factory-floor sensors, and the 12-bit resolution delivers 0.024% quantization step for 2 V full-scale inputs. Parallel CMOS outputs simplify FPGA interface, allowing 80 MSPS aggregate throughput when both channels run continuously.
推荐
Portable Instrumentation
Battery-powered test and measurement equipment benefits from the AD9238BSTZ-40's 330 mW dissipation at 40 MSPS, which keeps thermal management simple and extends battery life versus faster ADCs. The 3.3 V single-supply operation simplifies power-tree design, and the small 7x7 mm LQFP package fits handheld form factors. Each of the two channels can sample a different signal simultaneously, doubling oscilloscope or spectrum-analyzer channel count without doubling board area.
推荐
Radar and Lidar Signal Processing
Pulsed radar and lidar receivers digitize the reflected pulse shape with high dynamic range; the AD9238BSTZ-40's 70 dBFS SNR with differential inputs captures both close-range returns and weak distant targets in the same capture frame. Dual-channel sampling supports coherent I/Q processing across quadrature demodulated echoes. The pipelined architecture's inherent latency is acceptable for non-real-time DSP pipelines where precise amplitude measurement matters more than minimal delay.
推荐
Software-Defined Radio (SDR) Baseband
SDR platforms use the AD9238BSTZ-40 to sample I and Q baseband signals after the quadrature demodulator. Both channels share a common clock input, preserving phase coherence essential for digital demodulation of phase-modulated schemes such as QPSK and QAM. The 40 MSPS throughput handles wideband signals up to 18 MHz in the digital domain, while the 64-LQFP footprint simplifies custom SDR front-end boards built around it.
推荐
Touchscreen and Image-Sensor Front-End
Digital X-ray flat-panel detectors and machine-vision cameras use the AD9238BSTZ-40's dual channels to digitize adjacent sensor rows simultaneously, halving the analog trace routing and reducing cross-channel timing skew. The 12-bit dynamic range captures the full contrast range of CCD and CMOS image sensor outputs, and the integrated reference removes one external component, saving BOM cost in space-constrained modules.
推荐
推荐产品汇总
工程参考数据： AD9238BSTZ-40 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD9238BSTZ-65 | AD9238BSTZ-20 | AD9248BSTZ-40 | AD9248BSTZ-65 | AD9238BSTRL-40 | AD9238BST-65 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-LQFP (7x7 mm) | 64-LQFP (7x7 mm) - same | 64-LQFP (7x7 mm) - same | 64-LQFP (7x7 mm) - same | 64-LQFP (7x7 mm) - same | 64-LQFP (7x7 mm) - same | 64-LQFP (7x7 mm) - same |
| Resolution | 12 bit | 12 bit - same | 12 bit - same | 14 bit - higher | 14 bit - higher | 12 bit - same | 12 bit - same |
| Max Sample Rate | 40 MSPS | 65 MSPS (+62.5%) | 20 MSPS (-50%) | 40 MSPS - same | 65 MSPS (+62.5%) | 40 MSPS - same | 65 MSPS (+62.5%) |
| Power Consumption | 330 mW at 40 MSPS | 600 mW (+82%) | 180 mW (-45%) | 330 mW - same | 720 mW | 330 mW - same | 600 mW |
| Number of Channels | 2 (dual) | 2 - same | 2 - same | 2 - same | 2 - same | 2 - same | 2 - same |
| Supply Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V - same | 2.7 V to 3.6 V - same | 2.7 V to 3.6 V - same | 2.7 V to 3.6 V - same | 2.7 V to 3.6 V - same | 2.7 V to 3.6 V - same |
| RoHS Compliant | Yes (Z suffix) | Yes (Z suffix) | Yes (Z suffix) | Yes (Z suffix) | Yes (Z suffix) | Yes (Z suffix) | No (non-RoHS BST) |
| Pin-to-Pin Compatible | Reference | Yes | Yes | Yes (different family but same pinout) | Yes | Yes | Yes |
关键差异点
- Pin-compatible 14-bit upgrade path （对比 AD9248BSTZ-40)
- Three speed grades from single PCB layout （对比 AD9238BSTZ-20 / AD9238BSTZ-65)
- Integrated voltage reference eliminates external VREF component （对比 TI ADS6225)
设计说明
Route the differential analog inputs (AINA+ / AINA- and AINB+ / AINB-) as matched-length 100 ohm differential traces to the analog pins, keeping them short and isolated from noisy digital traces. Each AVDD and DRVDD pin must have its own 0.1 uF X7R ceramic decoupling capacitor placed within 5 mm, plus a 10 uF bulk tantalum nearby. The exposed thermal pad under the LQFP must be soldered to a continuous ground plane for thermal relief; the device dissipates up to 330 mW at 40 MSPS and requires the full copper area to remain within the -40C to +85C industrial temperature range.
Clock jitter is the primary limit on achievable SNR. The AD9238BSTZ-40's datasheet specifies that 70 dBFS SNR at 9.7 MHz input requires clock jitter below 0.5 ps RMS. Estimated impact: increasing jitter to 1 ps RMS drops SNR by about 6 dB. Use a low-jitter clock source (such as a crystal oscillator or clock-cleaner IC) and avoid sharing the clock with switching regulators or fast digital logic. The on-chip duty-cycle stabilizer helps with moderate clock duty error but does not compensate for jitter.
Estimated: do not drive the analog inputs with single-ended signals - the ADC is fully differential and loses ~3 dB of dynamic range and degrades SFDR (spurious-free dynamic range) by 15 to 20 dB when a true differential driver is not used. Place an AD8138, ADA4940, or transformer between single-ended sources and the ADC inputs. Also note that the ADC's REGCOMD and REGFMD pins require external decoupling capacitors per the datasheet - omitting them reduces SNR and may cause output errors. Finally, the channel A and channel B clock traces should be matched-length so that both channels sample within 100 ps of each other; skew between channels destroys phase-coherent applications like I/Q demodulation.
合规信息
RoHS-compliant (Z suffix indicates lead-free) per Analog Devices product page. REACH unaffected per partgenie.ai data. AEC-Q100 not applicable for this commercial/industrial-grade ADC. Operating temperature range -40C to +85C. MSL 3 (168 hours) per JEDEC J-STD-020.
