ADC1113D125HN-C18 - Dual 11-bit 125MSPS JESD204A ADC | Renesas
料号： ADC1113D125HN-C18 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $72.1 | $721.00 |
| 100 | $64.85 | $6,485.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.75 | $52,750.00 |
ADC1113D125HN-C18 概述
A pipelined ADC is a high-speed analog-to-digital converter architecture that uses a cascade of low-resolution stages to digitize an analog signal at hundreds of millions of samples per second. Pipelined ADCs occupy the middle ground between successive-approximation register (SAR) ADCs (which prioritize DC accuracy at low speed) and flash ADCs (which provide single-cycle conversion but consume large die area). They are widely used in communications infrastructure, radar digitizers, and high-speed instrumentation where dynamic range and sample rate must be balanced against power dissipation.
Key features of the ADC1113D125HN-C18 include dual 11-bit resolution, 125 MSPS maximum conversion rate, JESD204A serial interface for reduced board routing, integrated SPI for register programming, and a 56-lead HVQFN package with exposed thermal pad. The split analog/digital supply architecture (3 V/1.8 V) lets system designers power the analog front-end cleanly while mating the digital output stage to lower-voltage FPGA transceivers without level shifters. An internal reference and input buffer simplify the external bill of materials.
Typical applications include multi-channel wireless base-station receivers, software-defined radio front-ends, medical imaging digitizers, radar signal conditioning, and high-speed data acquisition cards. The 125 MSPS sample rate pairs naturally with the JESD204A link bandwidth, and the dual-channel design allows I/Q sampling of intermediate-frequency signals directly at the antenna interface.
When designing with this part, route the analog and digital supplies separately and decouple each pin with a 100 nF ceramic capacitor. Place the decoupling capacitors as close as possible to the supply pins and stitch the exposed thermal pad to a continuous ground pour to achieve the rated thermal performance and reduce digital switching noise coupling into the analog inputs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on any single manufacturer or distributor page, giving engineers an information-gain advantage when sourcing the ADC1113D125HN-C18.
直接替换替代料： ADC1113D125HN-C18 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1113D125HN-C18 （相同外形与封装尺寸） ——差异在于 Package, Resolution, Number of Channels, RoHS Status, Architecture.
快速对比工具——选择替代料号进行并排对比：
ADC1112D125HN-C18
✅ 直接替换✓ 有现货
$9.48 / 个
查看数据手册 →ADC1113D125HN/C1
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC1113D125HN/C1:5
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC1113D125HN-C18 最大额定值与电气特性
| 分辨率 | 11 bits |
| Number of Channels | Dual (2) |
| Sample Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| Serial Interface | JESD204A |
| Configuration Interface | SPI (Serial Peripheral Interface) |
| Analog Supply Voltage | 3 V |
| Digital Output Supply Voltage | 1.8 V |
| 封装 | 56-VFQFN Exposed Pad (HVQFN) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
ADC1113D125HN-C18 引脚配置
| 引脚 1 | AVDD — Analog supply 3 V |
| 引脚 2 | AGND — Analog ground |
| 引脚 3 | AIN_AP — Channel A positive analog input |
| 引脚 4 | AIN_AN — Channel A negative analog input |
| 引脚 5 | AGND — Analog ground |
| 引脚 6 | AVDD — Analog supply 3 V |
| 引脚 7 | VCM_A — Channel A common-mode voltage output |
| 引脚 8 | AVDD — Analog supply 3 V |
| 引脚 9 | AGND — Analog ground |
| 引脚 10 | AIN_BP — Channel B positive analog input |
| 引脚 11 | AIN_BN — Channel B negative analog input |
| 引脚 12 | AGND — Analog ground |
| 引脚 13 | AVDD — Analog supply 3 V |
| 引脚 14 | VCM_B — Channel B common-mode voltage output |
| 引脚 15 | AGND — Analog ground |
| 引脚 16 | CLK_P — Differential clock input positive |
| 引脚 17 | CLK_N — Differential clock input negative |
| 引脚 18 | AGND — Analog ground |
| 引脚 19 | AVDD — Analog supply 3 V |
| 引脚 20 | NC — Not connected (per datasheet) |
| 引脚 21 | DOUT_A_P — JESD204A serial lane A positive |
| 引脚 22 | DOUT_A_N — JESD204A serial lane A negative |
| 引脚 23 | DVDD — Digital output supply 1.8 V |
| 引脚 24 | DGND — Digital ground |
| 引脚 25 | DOUT_B_P — JESD204A serial lane B positive |
| 引脚 26 | DOUT_B_N — JESD204A serial lane B negative |
| 引脚 27 | DVDD — Digital output supply 1.8 V |
| 引脚 28 | DGND — Digital ground |
| 引脚 29 | SYSREF_P — JESD204A system reference positive |
| 引脚 30 | SYSREF_N — JESD204A system reference negative |
| 引脚 31 | DVDD — Digital output supply 1.8 V |
| 引脚 32 | DGND — Digital ground |
| 引脚 33 | CSN — SPI chip select (active low) |
| 引脚 34 | SCLK — SPI serial clock |
| 引脚 35 | SDIO — SPI serial data in/out |
| 引脚 36 | SDO — SPI serial data out |
| 引脚 37 | RESETN — Hardware reset (active low) |
| 引脚 38 | DVDD — Digital output supply 1.8 V |
| 引脚 39 | DGND — Digital ground |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | DVDD — Digital output supply 1.8 V |
| 引脚 44 | DGND — Digital ground |
| 引脚 45 | AVDD — Analog supply 3 V |
| 引脚 46 | AGND — Analog ground |
| 引脚 47 | AVDD — Analog supply 3 V |
| 引脚 48 | VREF — Voltage reference pin |
| 引脚 49 | AGND — Analog ground |
| 引脚 50 | AVDD — Analog supply 3 V |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | AVDD — Analog supply 3 V |
| 引脚 54 | AGND — Analog ground |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | EP — Exposed thermal pad (must be soldered to AGND) |
典型应用
ADC1113D125HN-C18 适用于 6 应用s: Wireless Base-Station Receiver Digitiser, Software-Defined Radio Front End, Medical Ultrasound Beamformer, Radar Signal Conditioning, High-Speed Data Acquisition Card, Industrial Test & Measurement Instrumentation.
Wireless Base-Station Receiver Digitiser
The ADC1113D125HN-C18 is well suited to multi-channel wireless base-station receivers that require digitising I/Q baseband signals at intermediate frequencies up to 125 MSPS per channel. Its dual matched ADC channels allow direct I/Q sampling of an IF signal with matched gain and offset, while the integrated JESD204A serial output pairs naturally with an FPGA baseband processor. The 3 V analog supply keeps the input common-mode compatible with standard IF amplifier outputs. Compared with parallel-LVDS ADCs the JESD204A interface dramatically reduces PCB trace count, easing routing in dense multi-antenna MIMO front ends.
推荐
Software-Defined Radio Front End
Software-defined radio (SDR) platforms use the ADC1113D125HN-C18 to digitise RF or IF signals directly into FPGAs for digital demodulation. The dual 11-bit 125 MSPS channels capture I and Q simultaneously, eliminating skew between paths and simplifying the digital down-conversion pipeline. The integrated SPI interface lets the host software tune gain, offset, and clock delay on the fly, enabling adaptive front-end control. The exposed thermal pad and 56-VFQFN package allow compact SDR dongles and lab instrumentation where board area is constrained.
推荐
Medical Ultrasound Beamformer
In medical ultrasound beamforming the ADC1113D125HN-C18 digitises the receive channel I/Q signals after the analog front-end and beamformer summer. The 125 MSPS sample rate preserves full bandwidth of 5-10 MHz ultrasound probes with margin, and the dual-channel nature allows Q-channel data to be captured simultaneously with I-channel data for quadrature demodulation. Low latency JESD204A output reduces the delay between received echo and beamformed image, critical for real-time imaging. The 3 V analog supply maintains compatibility with low-noise ultrasound preamplifiers.
推荐
Radar Signal Conditioning
Radar systems use the ADC1113D125HN-C18 to digitise intermediate-frequency outputs from radar mixers in surveillance, automotive, and weather radar applications. Dual matched channels simplify I/Q demodulation of Doppler-shifted echoes, and the 11-bit resolution is sufficient for envelope detection and MTI filtering. JESD204A serial output lowers EMC emissions by avoiding wide parallel buses that would otherwise radiate RF interference. The exposed thermal pad sustains 125 MSPS operation at industrial ambient temperatures typical of automotive and outdoor radar installations.
推荐
High-Speed Data Acquisition Card
PCIe and PXIe data acquisition cards employ the ADC1113D125HN-C18 as the front-end digitiser when 125 MSPS dual-channel sampling is required. Each card typically pairs one ADC1113D125 with a JESD204A-capable FPGA, with the FPGA performing DMA into host memory. The 56-VFQFN footprint allows dense card layouts where multiple ADC channels sit side by side along a single FPGA. SPI programming enables factory calibration routines to correct gain and offset across all populated channels.
推荐
Industrial Test & Measurement Instrumentation
Bench oscilloscopes, spectrum analysers, and protocol analysers use the ADC1113D125HN-C18 for wide-bandwidth signal capture up to 125 MSPS. Dual matched channels allow time-interleaved sampling when two devices are clocked in quadrature, effectively doubling the sample rate. The integrated SPI and 1.8 V digital rail simplify integration with modern FPGA-based instruments. Industrial users benefit from the surface-mount HVQFN package, which is compatible with standard reflow processes and supports long-term reliability targets.
推荐
推荐产品汇总
工程参考数据： ADC1113D125HN-C18 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1112D125HN-C18 | ADC1113D125HN/C1 | ADC1113D125HN/C1:5 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFN Exposed Pad (HVQFN) | 56-VFQFN Exposed Pad (HVQFN) - same | 56-VFQFN Exposed Pad (HVQFN) - same | 56-VFQFN Exposed Pad (HVQFN) - same |
| Resolution | 11 bits | 12 bits | 11 bits | 11 bits |
| Number of Channels | Dual (2) | Dual (2) | Dual (2) | Dual (2) |
| Sample Rate (max) | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Serial Interface | JESD204A | JESD204A | JESD204A | JESD204A |
| Analog Supply Voltage | 3 V | 3 V | 3 V | 3 V |
| Digital Output Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
关键差异点
- Dual matched channels at 125 MSPS in a single 56-VFQFN package （对比 ADC1112D125HN-C18)
- Integrated JESD204A serial interface （对比 Parallel LVDS ADCs)
- Split 3 V analog / 1.8 V digital supplies （对比 Single 3.3 V supply ADCs)
设计说明
Route the 3 V analog supply (AVDD) and 1.8 V digital supply (DVDD) on separate PCB planes joined only at a single ferrite bead or pi-filter at the regulator boundary. Place a 100 nF ceramic decoupling capacitor as close as possible to each AVDD and DVDD pin, and add a 10 uF bulk capacitor near the device. This star-grounding strategy prevents digital switching noise from coupling back into the analog front end through shared supply impedance.
The 56-VFQFN exposed thermal pad must be soldered to a continuous ground pour that extends at least 8 thermal vias into an inner ground plane. This is essential for removing the heat from both ADC channels at full 125 MSPS sample rate, and prevents intermittent latch-up or shutdown events. Maintain 50 ohm controlled-impedance routing on the JESD204A differential pairs (DOUT_A_P/N, DOUT_B_P/N, SYSREF_P/N) with length matching to within 100 mil to avoid lane-to-lane skew.
Do not apply an analog input common-mode voltage outside the datasheet-specified range or the input ESD diodes will forward-bias and add distortion to the digitised signal. The VCM_A and VCM_B outputs are useful as a clean reference for driving transformer-coupling networks, but they cannot source more than a few milliamps. Always assert RESETN after power-up and follow the datasheet's JESD204A link-initialisation sequence (ILAS) before sampling real data; otherwise the lanes may return K28.5 characters instead of valid samples.
合规信息
RoHS and lead-free status per Renesas/IDT product page. AEC-Q100 qualification status not stated in available data - contact Renesas for automotive-grade ordering codes.
