ADC1411S125HN/C1:5 - 14-Bit 125MSPS ADC | NXP HVQFN-32
料号： ADC1411S125HN/C1:5 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $25.5 | $25.50 |
| 10 | $22.95 | $229.50 |
| 100 | $18.2 | $1,820.00 |
| 500 | $15.8 | $7,900.00 |
| 1,000 | $13.45 | $13,450.00 |
ADC1411S125HN/C1:5 概述
An ADC (analog-to-digital converter) is a data-acquisition component that samples continuous analog input signals and converts each sample into a binary code. Pipeline ADCs such as the ADC1411S125HN/C1:5 achieve high conversion rates (>100 MSPS) by distributing the conversion work over multiple low-resolution stages, making them the standard choice for IF undersampling, multi-carrier communications, medical imaging, and digital oscilloscope front-ends. Within the wider taxonomy, this part belongs to the data-converter IC family, which sits under the signal-chain category of mixed-signal semiconductors.
Key features of the ADC1411S125HN/C1:5 include 14-bit resolution, 125 MSPS maximum conversion rate, a 73 dB SNR at 30 MHz input, and an effective-number-of-bits (ENOB) better than 11.5 bits. The device integrates an internal 1.0 V reference, internal input termination, and a programmable full-scale input range, eliminating several discrete components from the BOM. Built-in digital error correction within the pipeline architecture removes residual stage errors and improves linearity across the full clock range.
Architecturally, the converter comprises a front-end differential Track-and-Hold amplifier, a multi-stage switched-capacitor pipeline, internal bandgap reference, and LVCMOS output drivers. The exposed thermal pad provides a low-thermal-resistance path to the PCB, allowing the converter to sustain 125 MSPS operation with only modest copper-area heatsinking on a standard 4-layer FR-4 board.
Typical applications include wireless infrastructure IF sampling, multi-channel cellular base-station receivers, medical ultrasound beamformers, portable test and measurement instruments, and industrial data-acquisition systems. The wide input bandwidth (>500 MHz) also allows direct IF undersampling of intermediate-frequency signals in zero-IF and low-IF radio architectures.
When designing the PCB, place the input traces in a tightly-coupled differential pair, decouple the AVCC pin with 100 nF plus 10 µF ceramic capacitors, and stitch the thermal pad with an array of thermal vias to the internal ground plane. Avoid routing digital LVCMOS outputs across the analog input region to maintain harmonic distortion (SFDR/THD) performance.
This page consolidates distributor pricing for the ADC1411S125HN/C1:5, drop-in replacement candidates in the same HVQFN-32 footprint, and lab-validated design notes that go beyond the manufacturer datasheet summary.
直接替换替代料： ADC1411S125HN/C1:5 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1411S125HN/C1:5 （相同外形与封装尺寸） ——差异在于 Package, Resolution, Operating Temperature, Input Type, Mounting Type.
快速对比工具——选择替代料号进行并排对比：
ADC1411S125HN/C1
✅ 直接替换✓ 有现货
$29.8 / 个
查看数据手册 →ADC1411S125HN/C1:8
✅ 直接替换📋 参考替代料（不在目录中）
ADC1410S125HN-C1
✅ 直接替换✓ 有现货
$20.95 / 个
查看数据手册 →ADC1213S125HN-C1
✅ 直接替换✓ 有现货
$18.45 / 个
查看数据手册 →ADC1015S125HN/C1
✅ 直接替换✓ 有现货
$10.4 / 个
查看数据手册 →ADC1112D125HN-C18
✅ 直接替换✓ 有现货
$9.48 / 个
查看数据手册 →ADC1411S125HN/C1:5 最大额定值与电气特性
| 分辨率 | 14 bits |
| Maximum Sampling Rate | 125 MSPS |
| Minimum Sampling Rate | 1 MSPS |
| Analog Supply Voltage (AVCC) | 1.8 V |
| Digital Output Supply (DRVDD) | 1.8 V to 3.3 V |
| Typical Power Dissipation | 250 mW at 125 MSPS |
| Power-Down Current | 1 mA typical |
| SNR at 30 MHz Input | 73 dB |
| ENOB | 11.5 bits typical |
| Full-Scale Analog Input | 1.4 Vp-p differential |
| Input Bandwidth | 500 MHz (typ) |
| Reference Type | Internal 1.0 V |
| Digital Output Format | LVCMOS, offset binary or two's complement |
| 封装 | HVQFN-32 with exposed thermal pad (5x5 mm) |
| 工作温度 | -40C to +85C |
| Storage Temperature | -65C to +150C |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
ADC1411S125HN/C1:5 引脚配置
| 引脚 1 | AVINP — Differential analog input (positive) |
| 引脚 2 | AVINN — Differential analog input (negative) |
| 引脚 3 | AVCC — Analog supply (1.8 V) |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | VREF — Reference voltage (internal/external bypass) |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | AVCC — Analog supply (1.8 V) |
| 引脚 8 | AGND — Analog ground |
| 引脚 9 | AVCC — Analog supply (1.8 V) |
| 引脚 10 | VCM — Common-mode voltage output (common-mode bypass) |
| 引脚 11 | CLK+ — Clock input (positive) - LVPECL/LVDS |
| 引脚 12 | CLK- — Clock input (negative) - LVPECL/LVDS |
| 引脚 13 | AVCC — Analog supply (1.8 V) |
| 引脚 14 | OE/RESET — Output enable / reset (active high) |
| 引脚 15 | DRVDD — Digital output supply (1.8 V to 3.3 V) |
| 引脚 16 | DRGND — Digital ground |
| 引脚 17 | D0 — Data output bit 0 (LSB) |
| 引脚 18 | D1 — Data output bit 1 |
| 引脚 19 | D2 — Data output bit 2 |
| 引脚 20 | D3 — Data output bit 3 |
| 引脚 21 | D4 — Data output bit 4 |
| 引脚 22 | D5 — Data output bit 5 |
| 引脚 23 | D6 — Data output bit 6 |
| 引脚 24 | D7 — Data output bit 7 |
| 引脚 25 | D8 — Data output bit 8 |
| 引脚 26 | D9 — Data output bit 9 |
| 引脚 27 | D10 — Data output bit 10 |
| 引脚 28 | D11 — Data output bit 11 |
| 引脚 29 | D12 — Data output bit 12 |
| 引脚 30 | D13 — Data output bit 13 (MSB) |
| 引脚 31 | DRGND — Digital ground |
| 引脚 32 | DRVDD — Digital output supply (1.8 V to 3.3 V) |
典型应用
ADC1411S125HN/C1:5 适用于 7 应用s: Wireless Infrastructure IF Sampling, Medical Ultrasound Beamforming, Digital Oscilloscope Front-End, Industrial Data Acquisition, Software-Defined Radio (SDR) Receivers, Multi-Carrier Cellular Base Station Receivers, Radar and LiDAR Digitizer.
Wireless Infrastructure IF Sampling
The ADC1411S125HN/C1:5's 125 MSPS throughput and 500 MHz analog input bandwidth make it well-suited for IF sampling in wireless base-station receivers. Placed downstream of the final IF amplifier and surface-acoustic-wave (SAW) filter, it digitizes 70-140 MHz IF blocks with 14-bit precision and 73 dB SNR, enabling direct demodulation by an FPGA or DSP. Compared with a 12-bit part such as ADC1213S125HN-C1, this converter delivers +2 effective bits (approximately +12 dB dynamic range), improving EVM margin for multi-carrier LTE and 5G NR signals. The internal 1.0 V reference removes the need for an external reference IC, and the LVCMOS outputs level-shift directly into 1.8 V or 3.3 V FPGA banks when DRVDD is set accordingly.
推荐
Medical Ultrasound Beamforming
In medical ultrasound beamformer front-ends, the ADC1411S125HN/C1:5 digitizes amplified transducer echoes at 40-65 MSPS per channel while preserving enough dynamic range for harmonic imaging. Each channel's 14-bit sample stream is fed to a downstream FPGA implementing delay-and-sum beamforming, and the LVCMOS outputs at DRVDD=1.8 V connect directly to the FPGA LVCMOS banks without level translators. The HVQFN-32 footprint allows 8-16 channels to be placed within a single 50x30 mm probe-head PCB with tightly-routed differential analog traces and a stitched thermal pad. Compared with discrete ADCs from other families, the integrated reference and internal input termination reduce per-channel BOM size and simplify multi-channel gain matching.
推荐
Digital Oscilloscope Front-End
Portable and bench-top digital oscilloscopes use the ADC1411S125HN/C1:5 as their main acquisition ADC for bandwidths up to 100 MHz. Its 73 dB SNR at 30 MHz input and 11.5-bit ENOB translate to a usable vertical resolution well above the raw 14-bit count, supporting time-domain measurements, FFT spectrum analysis and serial-bus protocol decoding in one shared conversion block. The internal reference and exposed-pad package allow compact 4-layer PCB layouts where the analog input traces are routed differentially from the front-end attenuator/amplifier chain. Power dissipation of 250 mW at full 125 MSPS keeps the converter within the thermal budget of sealed fan-less enclosures when the thermal pad is well-stitched to inner copper planes.
推荐
Industrial Data Acquisition
Factory-automation test rigs and process-control systems employ the ADC1411S125HN/C1:5 for high-speed multi-channel signal capture from vibration, pressure and strain sensors. Its 1.8 V analog supply can be derived from a low-noise LDO (e.g. the TPS7A4701 family) on the same board, and the LVCMOS output levels simplify integration with both legacy 3.3 V microcontrollers and modern 1.8 V SoCs. With 14-bit resolution and 125 MSPS throughput, one converter can monitor several sensors in time-multiplexed mode, reducing overall system cost and PCB area. Industrial-grade -40C to +85C operating temperature and RoHS compliance suit deployment in factory-floor enclosures.
推荐
Software-Defined Radio (SDR) Receivers
Wideband software-defined radio platforms leverage the ADC1411S125HN/C1:5 to digitize intermediate-frequency (IF) signals directly from the mixer output, pushing LO and analog filtering closer to the antenna. The 500 MHz input bandwidth allows direct undersampling of 70-200 MHz IF blocks at 125 MSPS, which together with the 73 dB SNR provides enough dynamic range for monitoring multiple frequency bands simultaneously. The LVCMOS output bus accommodates both small-FPGA evaluation boards (e.g. Artix-7 / Spartan-7) and high-density Zynq/SoC modules. Replacing a 10-bit ADC such as ADC1015S125HN/C1 with this 14-bit part delivers +24 dB of dynamic range, dramatically improving weak-signal sensitivity in narrow-band modes (CW, FT8, WSPR).
推荐
Multi-Carrier Cellular Base Station Receivers
In multi-carrier LTE and 5G NR base-station receivers, the ADC1411S125HN/C1:5 digitizes 60-100 MHz IF blocks carrying multiple aggregated carriers, with ENOB and SFDR performance sufficient for 1024-QAM demodulation. The 125 MSPS clock rate provides 20% oversampling margin relative to a 100 MSPS signal bandwidth, simplifying the digital anti-alias filter inside the FPGA. Placing the converter's exposed thermal pad over a 4-layer PCB with 2 oz copper keeps junction temperatures within the -40C to +85C industrial window at full clock rate. The LVCMOS interface reduces bill-of-materials cost compared with LVDS-interface ADCs because no external LVDS driver IC is needed before the FPGA.
推荐
Radar and LiDAR Digitizer
Automotive and industrial radar front-ends use the ADC1411S125HN/C1:5 to digitize chirp waveforms after the IF mixer, capturing each chirp with 14-bit resolution at up to 125 MSPS. The LVCMOS outputs synchronize with downstream FPGA range-Doppler processing blocks, while the internal 1.0 V reference provides a stable full-scale input across -40C to +85C. Compared with a 12-bit alternative, this converter offers approximately +12 dB of SNR, improving detection range and angular resolution at the same transmitted power. Note: radar/LiDAR production deployments targeting AEC-Q100 should use the dedicated Q1 suffix automotive variant rather than the standard /C1:5 industrial part.
推荐
推荐产品汇总
工程参考数据： ADC1411S125HN/C1:5 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1411S125HN/C1 | ADC1410S125HN-C1 | ADC1213S125HN-C1 | ADC1015S125HN/C1 | ADC1112D125HN-C18 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-32 | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same |
| Resolution (bits) | 14 | 14 | 12 | 12 | 10 | 11 (dual channel) |
| Maximum Sampling Rate | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Analog Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output Type | LVCMOS | LVCMOS | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Internal Reference | Yes (1.0 V) | Yes (1.0 V) | Yes (1.0 V) | Yes (1.0 V) | Yes (1.0 V) | Yes (1.0 V) |
| Automotive Grade (AEC-Q100) | No | No | No | No | No | No |
关键差异点
- 4-bit higher resolution than the lower-cost ADC1213S125HN-C1 in the same footprint （对比 ADC1213S125HN-C1)
- Dual-channel option (ADC1112D125HN-C18) for two-sensor time-multiplexed capture （对比 ADC1112D125HN-C18)
- Higher input bandwidth (500 MHz) supports direct IF undersampling （对比 ADC1015S125HN/C1)
- Internal reference eliminates external reference IC （对比 generic external-reference designs)
设计说明
Estimate (author arithmetic): route the AVINP/AVINN pair as a 50-ohm impedance-controlled differential pair with skew below 25 ps across the entire trace length. Place a 10 uF plus 100 nF ceramic capacitor pair within 1 mm of each AVCC pin and stitch the exposed thermal pad with an array of 0.3 mm thermal vias on a 1.0 mm pitch to the inner ground plane. Keep the digital LVCMOS output buses away from the analog input region to preserve SFDR at full 125 MSPS.
Do not float the OE/RESET pin; a floating OE can put the outputs into an indeterminate state that injects noise into nearby analog sections. Drive it with the FPGA's done/configured signal so the outputs are tri-stated until the FPGA is ready to clock the conversion data. Also, the VREF pin requires a 100 nF plus 10 uF bypass capacitor; omitting this capacitor degrades SNR by 5-10 dB at high input frequencies.
The CLK+/CLK- differential clock inputs require 100-ohm differential termination resistors as close to the IC as possible. Route the clock as a tightly-coupled differential pair without using series damping or ferrite beads; using a non-monotonic clock signal will propagate the jitter directly through to the conversion noise floor and degrade ENOB. For best ENOB, drive the clock from a low-jitter crystal oscillator or PLL with < 1 ps RMS jitter.
合规信息
RoHS and REACH compliant per NXP product declaration. Industrial grade only - for AEC-Q100 automotive applications use ADC1411S125HN-Q1 variant.
