ADF4002BRUZ - 400 MHz Integer-N PLL | Analog Devices
料号： ADF4002BRUZ ✓ 量产中ADF4002BRUZ 概述
An integer-N PLL frequency synthesizer is a clock-and-timing semiconductor that locks an output frequency to a stable reference by comparing phase and frequency through a phase-frequency detector. A charge pump converts the detected error into a control voltage for a voltage-controlled oscillator, while programmable dividers establish the integer multiplication ratio. This architecture places the ADF4002 within the hierarchy of PLL, frequency synthesizer, clock generator, timing IC, and clock-and-timing semiconductor.
The principal features include 400 MHz bandwidth, operation from a 3.3 V supply, a separate charge-pump supply that permits an extended tuning-voltage range, programmable charge-pump currents, and a 3-wire serial interface. A 14-bit reference counter supports programmable reference-frequency division, while the programmable N divider establishes the synthesis ratio used to derive the output frequency. These functions support direct digital control of frequency and phase in RF signal chains.
The phase-frequency detector compares the divided reference signal with the divided feedback signal, and the charge pump generates the loop-control current required to null the phase and frequency error. The separate VP connection decouples the charge-pump voltage range from the main 3.3 V analog supply. This architecture is useful when a designer needs additional tuning-voltage headroom or a specific programmable charge-pump setting to balance loop bandwidth, reference phase noise, and settling behavior.
Typical uses include wireless receiver and transmitter local oscillators, up-conversion and down-conversion sections, instrumentation requiring stable synthesized frequencies, and test equipment requiring a programmable clock. The 16-lead TSSOP package also supports compact, surface-mount designs where the board area must remain small without adopting a larger land pattern.
For a new layout, preserve the manufacturer reference-network and decoupling topology, place the reference and feedback paths away from switching-node and charge-pump return currents, and verify loop settling with the intended reference frequency and divider settings. The available pin and electrical details should be taken directly from the pin-description and application tables in the ADF4002 manufacturer datasheet.
This page combines the device function, verified product characteristics, application guidance, pricing workflow, and engineering trade-offs in one engineering-focused reference. It also distinguishes the 16-lead TSSOP implementation from other package options without treating a different package as a drop-in replacement.
直接替换替代料： ADF4002BRUZ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
该产品暂无直接替换替代料。
请求替代料ADF4002BRUZ 规格参数
| Product Type | Integer-N PLL frequency synthesizer and phase detector |
| Maximum Operating Frequency | 400 MHz |
| Operating Frequency Range | 5 MHz to 400 MHz |
| Power Supply Voltage | 3.3 V |
| Charge Pump Supply | Separate VP supply |
| Charge Pump Current | Programmable |
| Reference Counter Resolution | 14 bits |
| N Divider | Programmable |
| Serial Interface | 3-wire |
| Phase-Frequency Detector | Low-noise digital phase-frequency detector |
| 封装 | 16-lead TSSOP |
| Package Width | 4.40 mm |
| Package Body Length | 0.173 inch |
| 安装类型 | Surface mount |
| RoHS 状态 | Compliant |
| REACH Status | Unaffected |
| Moisture Sensitivity Level | MSL 1, unlimited floor life |
ADF4002BRUZ 0.173 inch 引脚配置指南
ADF4002BRUZ（0.173 inch 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： ADF4002BRUZ.
请参阅 数据手册 以查看完整引脚配置。
典型应用
ADF4002BRUZ 适用于 6 应用s: Wireless Receiver Local Oscillator, Wireless Transmitter Up-Conversion, Precision Instrumentation Clock, Frequency-Selective Test Equipment, Phase-Coherent RF Signal Source, Communications Equipment Frequency Synthesis.
Wireless Receiver Local Oscillator
The ADF4002BRUZ fits a wireless receiver local-oscillator block because it supports operation from 5 MHz to 400 MHz and includes programmable reference and N dividers. The 14-bit reference counter and 3-wire programming interface allow the receiver's desired channel frequency to be loaded digitally while the phase-frequency detector and charge pump maintain phase alignment with the reference. The 16-lead TSSOP keeps the implementation compact, although the actual LO also requires a suitable VCO, loop filter, matching network, and controlled reference source. Because the separate VP connection supports an extended tuning-voltage range, it can help designers accommodate VCO tuning requirements without changing the main 3.3 V device supply.
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Wireless Transmitter Up-Conversion
ADF4002BRUZ can provide the programmable frequency reference used in a transmitter up-conversion chain. Its maximum operating frequency of 400 MHz, programmable charge-pump currents, and programmable N divider support a phase-locked synthesis architecture that derives an output signal from a stable reference. The 3-wire serial interface simplifies digital control from a transmitter controller, while the 3.3 V main supply simplifies integration with conventional low-voltage control electronics. The separate VP charge-pump supply should be dimensioned against the chosen VCO tuning voltage and loop requirements, and the RF output path still requires correct impedance matching and isolation.
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Precision Instrumentation Clock
The ADF4002BRUZ is suitable for instrumentation that requires a programmable, reference-locked signal instead of a fixed crystal oscillator. The integer-N architecture combines a 14-bit reference counter with a programmable N divider, allowing the desired output relationship to be established through the serial interface. This makes the device relevant to signal generators, frequency counters, measurement interfaces, and laboratory equipment. The design benefit is repeatability: once the loop is locked, output phase and frequency remain tied to the reference rather than drifting independently. The trade-off is the need to design and validate the loop filter against the intended reference and VCO, particularly when low phase noise or fast settling is required.
推荐
Frequency-Selective Test Equipment
A programmable PLL can simplify RF test equipment that must generate multiple frequencies while preserving phase coherence with a laboratory reference. ADF4002BRUZ offers a 400 MHz maximum operating frequency, programmable dividers, and programmable charge-pump currents, giving the instrument designer control over synthesis ratio and loop dynamics. The 16-lead TSSOP footprint supports compact instrument electronics without using a larger package. For this use case, evaluate phase noise, lock time, reference spur levels, and output amplitude alongside frequency range. Those performance results depend on the complete loop-filter and VCO implementation, so a nominal 400 MHz device rating should not be treated as a complete signal-chain specification.
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Phase-Coherent RF Signal Source
ADF4002BRUZ can serve as the locking element of a phase-coherent RF source in which several outputs must share a stable frequency relationship. Its digital phase-frequency detector compares reference and feedback signals, while the charge pump drives the external VCO tuning network. Programmable charge-pump currents allow the loop bandwidth to be adjusted for the reference frequency, VCO gain, and required settling behavior. The 3-wire interface supports direct integration with embedded control logic, and the 14-bit reference counter offers flexible reference division. In a multi-channel instrument, separate reference distribution and careful isolation are still necessary to prevent common-reference coupling and channel-to-channel phase errors.
推荐
Communications Equipment Frequency Synthesis
The ADF4002BRUZ is appropriate for communications equipment that requires programmable local-oscillator or intermediate-frequency generation from a shared reference. Its 5 MHz to 400 MHz operating range covers the stated frequency-synthesis span, while programmable R and N dividers support multiple channel plans. The 3.3 V main supply and separate charge-pump supply allow the control circuitry and VCO tuning range to be handled according to their respective requirements. For production communications designs, validate lock range, reference spurs, phase noise, and channel-switching time over temperature and supply tolerance. The PLL should therefore be evaluated as a system with its reference, loop filter, VCO, and matching network rather than by bandwidth alone.
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推荐产品汇总
工程参考数据： ADF4002BRUZ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 |
|---|---|
| Product Type | Integer-N PLL frequency synthesizer and phase detector |
| Brand | Analog Devices |
| Package | 16-lead TSSOP |
| Maximum Operating Frequency | 400 MHz |
| Operating Frequency Range | 5 MHz to 400 MHz |
| Main Supply Voltage | 3.3 V |
| Charge Pump Supply | Separate VP supply |
| Reference Counter | 14-bit programmable R counter |
| Serial Interface | 3-wire |
| Charge Pump Current | Programmable |
关键差异点
- Compact 16-lead TSSOP implementation （对比 ADF4002BCPZ)
- Separate charge-pump supply supports extended tuning voltage （对比 ADF4002BCPZ)
- High-frequency programmable synthesis in a compact package （对比 ADF4002BCPZ)
设计说明
Use the Analog Devices ADF4002 manufacturer-datasheet reference circuit as the layout baseline. Keep the reference and feedback routes short, avoid routing them beside switching or high-current charge-pump paths, and return their grounds according to the recommended topology. The programmable R and N dividers and phase-frequency detector depend on clean edges, so route length and ground-current differences can affect spur and lock behavior even when the nominal clock is correct.
Treat the main 3.3 V supply and the separate VP charge-pump supply as distinct rails in the schematic and PCB. Decouple each rail at the appropriate device pins using the component and layout values specified by Analog Devices. Confirm the VP range against the external VCO tuning-voltage requirement before power-up; the separate VP function adds tuning flexibility, but an unsuitable charge-pump voltage can prevent proper VCO operation or reduce lock margin.
Do not treat any ADF4002 package option as a drop-in substitute. ADF4002BRUZ uses a 16-lead TSSOP, while ADF4002BCPZ uses a different 20-pin package. Before changing ordering codes, verify pin names, programming protocol, maximum frequency, supply limits, exposed-pad handling, land pattern, and reflow profile. A family-level similarity in frequency range or PLL architecture does not establish footprint compatibility.
Program the reference, N-divider, and charge-pump settings for the actual reference frequency and VCO rather than selecting values only from the maximum 400 MHz headline specification. Validate lock range, phase noise, reference spur level, and settling time across the intended frequency plan. Poor loop-filter matching or excessive reference-noise coupling can prevent acceptable performance even when the PLL reports a valid lock condition.
合规信息
RoHS compliance, REACH unaffected status, and MSL 1 unlimited floor life are identified for ADF4002BRUZ. Lead-free, halogen-free, conflict-minerals, and AEC-Q100 status are not established.
