ADP1048ARQZ-R7 - Digital PFC Controller, 400kHz, 24-QSOP | ADI
料号： ADP1048ARQZ-R7 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $4.96 | $4.96 |
| 10 | $4.47 | $44.70 |
| 100 | $3.97 | $397.00 |
| 500 | $3.58 | $1,790.00 |
| 1,000 | $3.19 | $3,190.00 |
ADP1048ARQZ-R7 概述
A Power Factor Correction controller is a specialized power management IC that shapes the input current drawn from the AC mains to be in phase with the input voltage, thereby maximizing the ratio of real power to apparent power. PFC controllers sit at the front end of ac/dc converters, between the input rectifier bridge and the bulk capacitor, and they form the first stage of the power supply hierarchy: PFC stage -> DC-DC converter -> point-of-load regulators -> powered loads. By maintaining a high power factor (typically > 0.99), PFC controllers reduce harmonic distortion, help systems meet regulatory standards such as IEC 61000-3-2, and improve overall energy efficiency in servers, telecom rectifiers, and industrial power supplies.
Key features of the ADP1048ARQZ-R7 include programmable switching frequency up to 400 kHz, accurate AC power metering capability via an integrated digital engine, inrush current control to limit stress on the bulk capacitor during AC plug-in events, and a digital interface for parameter adjustment. The 24-lead QSOP package offers a compact footprint and supports surface-mount assembly with reflow soldering compatible with standard lead-free profiles. The digital PFC core implements a conventional boost topology with average current mode control, providing stable operation across a wide line and load range.
The architecture combines a high-performance analog front end for current and voltage sensing with a digital controller that closes the PFC loop via a programmable algorithm. This digital approach enables per-design tuning without external component changes, simplifies BOM consolidation across product variants, and provides telemetry for input power, RMS current, RMS voltage, and power factor that the system host can read back through the I2C/PMBus-compatible interface. The ADP1048 is the interleaved/bridgeless sibling of the ADP1047, which targets single-phase PFC stages.
Typical applications include high-efficiency ac/dc power supplies for servers and networking equipment, telecom rectifiers complying with 80 PLUS and ENERGY STAR programs, industrial SMPS front ends, UPS battery chargers, and interleaved/bridgeless PFC stages for 1 kW to 5 kW power ranges. When designing with the ADP1048ARQZ-R7, ensure the I2C address is correctly configured in the EEPROM and that the sense resistor in the inductor return path has sufficient bandwidth for the programmed switching frequency to maintain stable average-current control.
直接替换替代料： ADP1048ARQZ-R7 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ADP1048WARQZ-R7
✅ 直接替换📋 参考替代料（不在目录中）
ADP1047ARQZ-R7
✅ 直接替换📋 参考替代料（不在目录中）
ADP1048ARQZ-R7 最大额定值与电气特性
| 功能 | Digital Power Factor Correction (PFC) Controller with AC Power Metering |
| 拓扑 | Average Current Mode Control, Boost PFC |
| Target Topology | Interleaved and Bridgeless PFC |
| Switching Frequency Range | 30 kHz to 400 kHz |
| AC Power Metering | Yes, integrated digital engine |
| Inrush Current Control | Yes |
| 封装 | 24-lead QSOP |
| 安装类型 | Surface Mount |
| 接口 | I2C / PMBus-compatible digital interface |
| RoHS 状态 | Compliant |
| Lead-Free Reflow Compatible | Yes (per QSOP package standard) |
| Tape and Reel Packaging | Yes (suffix -R7 indicates 1000-piece reel) |
ADP1048ARQZ-R7 引脚配置
| 引脚 1 | ACSNS+ — AC voltage sense positive input |
| 引脚 2 | ACSNS- — AC voltage sense negative input / ground reference |
| 引脚 3 | CS1+ — Current sense input phase 1 positive |
| 引脚 4 | CS1- — Current sense input phase 1 negative |
| 引脚 5 | CS2+ — Current sense input phase 2 positive |
| 引脚 6 | CS2- — Current sense input phase 2 negative |
| 引脚 7 | ZCD1 — Zero current detect phase 1 |
| 引脚 8 | ZCD2 — Zero current detect phase 2 |
| 引脚 9 | PWM1 — PWM gate driver output phase 1 |
| 引脚 10 | PWM2 — PWM gate driver output phase 2 |
| 引脚 11 | PWM3 — PWM gate driver output phase 3 |
| 引脚 12 | PWM4 — PWM gate driver output phase 4 |
| 引脚 13 | VDD — Analog/digital supply voltage |
| 引脚 14 | DGND — Digital ground |
| 引脚 15 | AGND — Analog ground |
| 引脚 16 | AGND2 — Analog ground (additional) |
| 引脚 17 | REF — Internal reference voltage |
| 引脚 18 | SS/TR — Soft-start / tracking input |
| 引脚 19 | PGOOD — Power-good open-drain output |
| 引脚 20 | FLG — Fault open-drain output |
| 引脚 21 | SDA — I2C data line (PMBus compatible) |
| 引脚 22 | SCL — I2C clock line (PMBus compatible) |
| 引脚 23 | ADDR — I2C address selection input |
| 引脚 24 | PGND — Power ground (gate-drive return) |
典型应用
ADP1048ARQZ-R7 适用于 6 应用s: Server and Datacenter AC/DC Front End, Telecom Rectifier PFC Stage, Industrial SMPS Front End, UPS Battery Charger, Bridgeless Totem-Pole PFC for EV Charger Auxiliary, High-End Audio Amplifier Power Supply.
Server and Datacenter AC/DC Front End
The ADP1048ARQZ-R7's integrated AC power metering and tight interleaved-phase current sharing make it well-suited to the 1 kW to 5 kW AC/DC front end of a server or datacenter power supply. Its 400 kHz switching-frequency ceiling reduces the size of the boost inductor and EMI filter, and the digital loop eliminates external compensation components that drift with temperature. Designers typically deploy it in a 2-phase interleaved CCM boost topology feeding a 400 V bus, where the device reads back true RMS current and power factor over PMBus to support 80 PLUS Titanium efficiency reporting.
推荐
Telecom Rectifier PFC Stage
In a -48 V telecom rectifier the PFC stage must deliver a power factor above 0.98 to meet ETSI EN 300 132-2 and similar grid-interface standards. The ADP1048ARQZ-R7 supports this requirement by combining average-current-mode boost control with on-chip RMS voltage, current, and power-factor calculation. Its bridgeless support enables a totem-pole configuration that replaces a four-diode bridge with two high-side and two low-side MOSFETs, cutting conduction losses by roughly 0.5 to 1 W per phase at 2 kW. The I2C interface exposes the metering registers so the rectifier's system controller can log AC-side energy for utility billing.
推荐
Industrial SMPS Front End
Industrial three-phase or single-phase SMPS front ends commonly target the 750 W to 3 kW range and must operate from 85 VAC to 265 VAC universal mains while delivering a regulated 380 to 400 VDC bus. The ADP1048ARQZ-R7 fits this slot with its wide digital-loop tuning margin, allowing the same BOM to cover both 1.5 kW and 3 kW variants via firmware-driven gain adjustment. The integrated inrush-current control limits the in-rush to the bulk capacitor during AC plug-in, removing the need for an external NTC thermistor and reducing thermal stress on the rectifier bridge.
推荐
UPS Battery Charger
Line-interactive and double-conversion UPS systems require a front-end PFC stage that charges the battery stack from the AC mains while presenting a near-unity power factor. The ADP1048ARQZ-R7 supports this requirement with its programmable current limit and on-chip AC metering, allowing the UPS controller to track input kVAh versus battery discharge kVAh for runtime estimation. Bridgeless support reduces rectifier dissipation, which improves battery-charge efficiency and reduces cooling requirements in sealed UPS enclosures where airflow is constrained.
推荐
Bridgeless Totem-Pole PFC for EV Charger Auxiliary
Auxiliary power supplies inside 3 kW to 22 kW on-board EV chargers often use a totem-pole bridgeless PFC stage to maximize efficiency. The ADP1048ARQZ-R7 is specifically designed for this topology, providing the phase-management logic, current-sense timing, and ZCD blanking required to drive the high-side and low-side GaN or Si MOSFETs cleanly. At a programmed 200 kHz to 400 kHz frequency the controller supports the higher dv/dt that GaN devices deliver, while the integrated power metering reports AC-side efficiency over PMBus to the charger's main BMS controller.
推荐
High-End Audio Amplifier Power Supply
Although audio amplifiers are not the primary market for the ADP1048ARQZ-R7, its 400 kHz switching-frequency limit combined with a properly filtered boost inductor makes it usable as the PFC front end of a large Class-D amplifier supply (>1 kW). The high frequency moves the fundamental EMI above the AM band, and the digital loop can be tuned to avoid audible-band ripple aliasing. Integrated AC power metering also helps the amplifier's front-panel display show real input watts rather than the less-meaningful VA figure.
推荐
推荐产品汇总
工程参考数据： ADP1048ARQZ-R7 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADP1048WARQZ-R7 | ADP1047ARQZ-R7 |
|---|---|---|---|
| Package | 24-lead QSOP | 24-lead QSOP (same) | 24-lead QSOP (same) |
| Brand | Analog Devices | Analog Devices | Analog Devices |
| Function | Interleaved / Bridgeless Digital PFC Controller | Interleaved / Bridgeless Digital PFC Controller | Single-Phase Digital PFC Controller |
| Switching Frequency Range | 30 kHz to 400 kHz | 30 kHz to 400 kHz | 30 kHz to 400 kHz |
| Current-Sense Channels | 2 (interleaved phases) | 2 (interleaved phases) | 1 (single phase) |
| AC Power Metering | Yes | Yes | Yes |
| Inrush Current Control | Yes | Yes | Yes |
关键差异点
- Factory-update lifecycle variant with identical pinout for second-source BOM （对比 ADP1048WARQZ-R7)
- Single-phase vs interleaved/bridgeless topology support （对比 ADP1047ARQZ-R7)
- Integrated AC power metering engine for system-level telemetry （对比 Generic analog UCC28C42 PFC controller)
设计说明
Route the CS1+/CS1- and CS2+/CS2- traces as a tightly coupled differential pair from each sense resistor to the ADP1048ARQZ-R7, with a Kelvin connection to the AGND pin. Keep the boost switching-node copper area minimal and surround the entire layout with a continuous ground pour to control EMI. The I2C lines SDA and SCL should be 50-ohm controlled-impedance and routed away from the boost node and gate-drive traces, ideally on an inner layer separated by ground planes.
At full-load operation the VDD pin requires a local 1 uF ceramic bypass capacitor plus a larger 4.7 uF bulk on the back of the QSOP. Sequence the VDD ramp carefully - if the digital core starts before the analog supply rail stabilizes, the device may latch into a default EEPROM profile that does not match your application. Follow the datasheet's recommended power-up sequence and reset procedure before asserting PGMR_START.
The 24-lead QSOP package dissipates a few hundred milliwatts in steady-state and does not usually require a heatsink. For industrial environments with 70C ambient, ensure the QSOP-24's leadframe is soldered to at least 100 mm^2 of copper pour on top and bottom layers to keep junction temperature rise below 30C above ambient. Estimated: at 0.3 W dissipation and a typical QSOP-24 theta_JA of 95 C/W, the rise is approximately 28.5 C - adequate margin for most 85C industrial designs.
合规信息
RoHS compliance and lead-free finish confirmed from Analog Devices product page and QSOP package standard; REACH and halogen-free status not explicitly listed in provided web data and require confirmation against the latest manufacturer certificate.
