ADS5102CPFB - 10-Bit 65MSPS 1.8V ADC | Texas Instruments
料号： ADS5102CPFB ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.4 | $8.40 |
| 10 | $7.55 | $75.50 |
| 100 | $6.7 | $670.00 |
| 500 | $6 | $3,000.00 |
| 1,000 | $5.4 | $5,400.00 |
ADS5102CPFB 概述
An analog-to-digital converter (ADC) is a data converter that translates continuous analog signals into discrete digital codes at a defined sampling rate. Pipelined ADCs are a popular architecture for high-speed, moderate-resolution conversion because they achieve high sampling rates (tens of MSPS to hundreds of MSPS) while keeping power and die area low. The ADS5102 belongs to the pipelined ADC product family within TI's data converter portfolio, sitting under the broader hierarchy of data converters -> signal chain -> mixed-signal semiconductors.
Key features include 65 MSPS sampling rate (versus 40 MSPS for the pin-compatible ADS5103), internal 1.8 V reference with optional external reference support, integrated sample-and-hold, single 1.8 V supply operation, and a power-down pin for battery-aware designs. Digital outputs are 3.3 V CMOS-compatible for direct connection to FPGAs, ASICs, or DSPs without level shifters.
Architecturally, the device uses multiple low-resolution pipeline stages that each quantize a residue, producing 10-bit output codes at the rated 65 MSPS throughput. The on-chip bandgap reference and proprietary calibration trim gain and offset across temperature.
Typical applications include CCD imaging front ends, baseband I/Q sampling for wireless receivers, video digitisation, portable instrumentation, and ultrasound receive channels. The wide input bandwidth and low 1.8 V supply current make the part attractive for handheld and field-portable designs.
When designing with the ADS5102CPFB, place the 0.1 uF + 10 uF decoupling network within 5 mm of each supply pin to suppress switching noise from the digital outputs. The internal reference is suitable for prototyping but should be bypassed with an external reference for production accuracy. Layout the differential input traces as a length-matched pair with characteristic impedance control to preserve SNR at the rated sample rate.
直接替换替代料： ADS5102CPFB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADS5102CPFB （相同外形与封装尺寸） ——差异在于 Package, Digital Supply Voltage, Reference, Resolution, Input Type.
快速对比工具——选择替代料号进行并排对比：
ADS5103CPFB
✅ 直接替换✓ 有现货
$6.95 / 个
查看数据手册 →ADS5102CPFBG4
✅ 直接替换✓ 有现货
$5.4 / 个
查看数据手册 →ADS5102IPFB
✅ 直接替换📋 参考替代料（不在目录中）
ADS5102IPFBG4
✅ 直接替换✓ 有现货
$5.75 / 个
查看数据手册 →ADS5102IPFBR
✅ 直接替换✓ 有现货
$5.05 / 个
查看数据手册 →ADS5102CPFB 最大额定值与电气特性
| 分辨率 | 10 bit |
| 采样率 | 65 MSPS |
| Architecture | Pipelined |
| Number of Input Channels | 1 |
| Input Type | Differential |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Digital Output Logic Level | 3.3 V CMOS-compatible |
| Data Interface | Parallel |
| Reference Type | Internal / External |
| Sample-and-Hold | Integrated |
| Power-Down Mode | Yes |
| 封装 | 48-TQFP (PFB) 7x7 mm |
| 安装类型 | Surface Mount |
ADS5102CPFB 引脚配置
| 引脚 1 | AVDD — Analog 1.8 V supply |
| 引脚 2 | AVDD — Analog 1.8 V supply |
| 引脚 3 | AGND — Analog ground |
| 引脚 4 | INP — Differential analog input (positive) |
| 引脚 5 | INN — Differential analog input (negative) |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | VREF — Reference voltage (internal/external) |
| 引脚 8 | REFM — Reference ground |
| 引脚 9 | REFP — Reference positive |
| 引脚 10 | AGND — Analog ground |
| 引脚 11 | CLKP — Differential clock input (positive) |
| 引脚 12 | CLKN — Differential clock input (negative) |
| 引脚 13 | AGND — Analog ground |
| 引脚 14 | PWDN — Power-down input (active high) |
| 引脚 15 | DGND — Digital ground |
| 引脚 16 | DVDD — Digital 1.8 V supply |
| 引脚 17 | DRDY — Data ready output |
| 引脚 18 | OE — Output enable |
| 引脚 19 | DGND — Digital ground |
| 引脚 20 | D9 — Data output bit 9 (MSB) |
| 引脚 21 | D8 — Data output bit 8 |
| 引脚 22 | D7 — Data output bit 7 |
| 引脚 23 | D6 — Data output bit 6 |
| 引脚 24 | D5 — Data output bit 5 |
| 引脚 25 | D4 — Data output bit 4 |
| 引脚 26 | D3 — Data output bit 3 |
| 引脚 27 | D2 — Data output bit 2 |
| 引脚 28 | D1 — Data output bit 1 |
| 引脚 29 | D0 — Data output bit 0 (LSB) |
| 引脚 30 | DGND — Digital ground |
| 引脚 31 | DVDD — Digital 1.8 V supply |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | DVDD — Digital 1.8 V supply |
| 引脚 35 | DGND — Digital ground |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | AVDD — Analog 1.8 V supply |
| 引脚 39 | AGND — Analog ground |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | AVDD — Analog 1.8 V supply |
| 引脚 43 | AGND — Analog ground |
| 引脚 44 | NC — Not connected (per datasheet) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | AVDD — Analog 1.8 V supply |
| 引脚 47 | AGND — Analog ground |
| 引脚 48 | AVDD — Analog 1.8 V supply |
典型应用
ADS5102CPFB 适用于 6 应用s: CCD Imaging Front End, Wireless Baseband I/Q Sampling, Video Digitisation, Portable Test and Measurement, Ultrasound Receive Channel, Industrial Control Data Acquisition.
CCD Imaging Front End
The ADS5102CPFB's 65 MSPS throughput and 10-bit resolution suit CCD line-scan and area-array imaging front ends where analog pixel data must be digitised at high frame rates. The 1.8 V analog/digital supply minimises power dissipation in densely packed camera head boards. The differential analog input rejects common-mode pickup from the CCD clock traces, while the parallel CMOS outputs stream data straight into an FPGA for pixel reconstruction. Designers typically drive the input through a differential amp or transformer to preserve the SNR budget.
推荐
Wireless Baseband I/Q Sampling
In baseband I/Q sampling chains for wireless receivers, the ADS5102CPFB digitises I or Q channels at baseband after quadrature demodulation. The 65 MSPS sample rate comfortably exceeds Nyquist for typical baseband bandwidths, while the 10-bit resolution is adequate for many narrowband and mid-bandwidth standards. The single 1.8 V supply simplifies power tree design in portable handsets. Differential inputs reject local-oscillator leakage at the demodulator output, improving effective SNR.
推荐
Video Digitisation
The ADS5102CPFB is well matched to standard-definition and lower-resolution video digitisation tasks where composite or component analog video must be sampled at 65 MSPS. The differential input accepts direct-coupled or AC-coupled video signals after a gain stage, and the parallel CMOS outputs deliver pixel data to a video processor or FPGA without level translation. Internal reference support reduces external BOM cost for cost-sensitive consumer video products.
推荐
Portable Test and Measurement
Handheld oscilloscope probes, spectrum analysers, and field-portable instruments use the ADS5102CPFB for digitising wideband analog signals at 65 MSPS with 10-bit resolution. The 1.8 V supply and integrated power-down mode extend battery life between charges. Differential inputs reject EMI pickup on long probe cables, while the small 48-TQFP footprint allows compact PCB layouts for portable enclosures. Internal reference support simplifies calibration-free prototyping.
推荐
Ultrasound Receive Channel
In low-end ultrasound receivers the ADS5102CPFB digitises the post-TGC analog receive signal at 65 MSPS, providing 10-bit resolution suitable for B-mode imaging. The differential input rejects common-mode noise from the transducer cable, while the integrated sample-and-hold captures fast echoes without external gating. Multiple ADS5102 channels can be paralleled across an FPGA for multi-element beamforming in compact cart-based ultrasound systems.
推荐
Industrial Control Data Acquisition
Industrial PLC analog input modules and high-speed process monitoring boards employ the ADS5102CPFB for digitising 4-20 mA loop or transducer signals at 65 MSPS. The 10-bit resolution suits many supervisory control tasks, while the 3.3 V CMOS outputs interface directly to industrial microcontrollers. Differential inputs reject switching noise from nearby motor drives and relay coils. Internal reference support reduces calibration drift in factory environments.
推荐
推荐产品汇总
工程参考数据： ADS5102CPFB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADS5103CPFB | ADS5102CPFBG4 | ADS5102IPFB | ADS5102IPFBG4 | ADS5102IPFBR |
|---|---|---|---|---|---|---|
| Package | 48-TQFP (PFB) 7x7 mm | 48-TQFP (PFB) 7x7 mm - same | 48-TQFP (PFB) 7x7 mm - same | 48-TQFP (PFB) 7x7 mm - same | 48-TQFP (PFB) 7x7 mm - same | 48-TQFP (PFB) 7x7 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 65 MSPS | 40 MSPS (-38%) | 65 MSPS | 65 MSPS | 65 MSPS | 65 MSPS |
| Analog Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Temperature Grade | Commercial | Commercial | Commercial | Industrial | Industrial | Industrial |
| Reference Type | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Highest 65 MSPS grade within the ADS510x family （对比 ADS5103CPFB)
- Differential analog input rejects common-mode noise （对比 ADS5102CPFBG4 (same die, reel variant))
- Industrial temperature grade option exists in same package （对比 ADS5102IPFB)
设计说明
Place a 0.1 uF X7R ceramic bypass capacitor within 2 mm of every AVDD and DVDD pin, and a single 10 uF tantalum or ceramic bulk capacitor near the supply pins. Estimated: with 5 AVDD and 5 DVDD pins tied together, total decoupling capacitance of roughly 6.0 uF + bulk is needed to keep digital switching noise below 50 mVpp on the analog rail. The 1.8 V analog and digital rails should be star-routed from a common ferrite bead to isolate high-frequency noise generated by the parallel CMOS outputs.
Route the differential analog input pair (INP/INN) and the differential clock pair (CLKP/CLKN) as 100 ohm differential length-matched traces with no more than 100 mil length mismatch. Keep digital output bus traces (D0-D9) and the DRDY strobe routed away from the analog input region to prevent digital-to-analog coupling. Use a continuous ground plane on the layer beneath the analog signals to provide a low-impedance return path and to minimise loop area for the high-speed switching currents.
Do not operate the ADS5102CPFB above the absolute maximum analog supply of 1.95 V or below 1.65 V - the device is not 3.3 V tolerant on AVDD/DVDD even though its outputs are 3.3 V CMOS-compatible. Do not leave the PWDN pin floating; tie it low through a 10 kohm resistor to enable normal operation. The internal reference is shared between analog and digital domains; if an external reference is used, ensure the reference decoupling caps are placed within 5 mm of the REFP/REFM pins to avoid reference-noise-induced gain error.
合规信息
RoHS, REACH, and lead-free status not present in the verified web data for ADS5102CPFB; status should be confirmed from the lot-specific manufacturer documentation when purchasing obsolete stock. AEC-Q100 not applicable (not an automotive-grade part).
