CD4017BF - 3-18V CMOS Decade Counter | TI | Sequencer
料号： CD4017BF ✓ 量产中CD4017BF 概述
A CMOS decade counter is a synchronous logic device that advances through a fixed number of states when triggered by an external clock. The CD4017 family combines an internal flip-flop and counter stages with ten decoded output lines. This places it in the logic IC, counter, divider, and sequencing-device hierarchy, where it bridges basic timing control and discrete state activation without requiring a microcontroller for simple ten-step sequences.
The CD4017BF provides three principal characteristics: a 3 V to 18 V supply range, ten decoded outputs, and a 16-pin PDIP package. Its broad supply range supports integration into legacy CMOS logic systems operating across multiple logic voltages. The decoded outputs can drive indicator stages, relays, transistors, or other circuit blocks when correctly interfaced, while the reset and clock-inhibit inputs provide basic sequence control.
Internally, the device uses the CD4000 CMOS logic family and counts upward. A rising clock edge advances the counter state, while the decoded outputs indicate the current count. The separate clock and clock-inhibit inputs allow an external signal to pause or inhibit progression, and the reset input returns the sequence to its initial state. Designers should account for propagation delay and supply-level timing when cascading counters or synchronizing outputs with other logic.
Typical uses include ten-step relay sequencing, bidirectional LED animation, programmable pulse-counting modules, divide-by-ten clock generation, and basic industrial control panels. In motor-control applications, decoded outputs can select winding drive stages or external switching elements. In indicator circuits, only the output corresponding to the active count is asserted, reducing the control logic required for a repeating visual pattern.
Design the clock source to provide clean, repeatable edges and respect the device’s absolute-maximum ratings. Use pull-up or pull-down resistors where an input may float, and ensure that reset and clock-inhibit signals cannot contend with external drivers. Decoupling capacitors should be placed close to the supply pins, while high-current loads should be driven through suitable transistors rather than loading the counter outputs directly.
This product page combines the TI product description, package information, decoded-counter functionality, practical design guidance, sourcing-oriented commercial answers, and clearly qualified replacement analysis. It is intended to help engineers confirm the CD4017BF fit, inspect its 16-pin connectivity, and decide whether a verified same-footprint alternative is appropriate for an existing PCB.
直接替换替代料： CD4017BF ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CD4017BF （相同外形与封装尺寸） ——差异在于 Logic Family, Number of Decoded Outputs.
CD4017BE
✅ 直接替换联系询价
查看数据手册 →HEF4017BP
✅ 直接替换📋 参考替代料（不在目录中）
MC14017BCP
✅ 直接替换📋 参考替代料（不在目录中）
CD4017BF 最大额定值与电气特性
| Logic Type | CMOS decade counter and divider |
| Logic Family | CD4000 |
| Counter Type | Decade |
| Number of Decoded Outputs | 10 outputs |
| Number of Counter Bits | 10-bit decoded counter |
| Counting Sequence | Up |
| Counting Method | Synchronous |
| 工作电源电压 | 3 V to 18 V |
| Package Type | PDIP-16 |
| 引脚数 | 16 pins |
| 安装方式 | Through-hole |
| 输出配置 | 10 decoded outputs |
| Clock Input | 1 clock input |
| Clock Inhibit Input | 1 clock inhibit input |
| Reset Input | 1 reset input |
CD4017BF 引脚配置
| 引脚 1 | CLK — Clock input |
| 引脚 2 | CL INH — Clock inhibit input |
| 引脚 3 | RESET — Asynchronous reset input |
| 引脚 4 | Q4 — Decoded output 4 |
| 引脚 5 | Q5 — Decoded output 5 |
| 引脚 6 | Q6 — Decoded output 6 |
| 引脚 7 | Q7 — Decoded output 7 |
| 引脚 8 | VSS — Ground supply |
| 引脚 9 | Q8 — Decoded output 8 |
| 引脚 10 | Q9 — Decoded output 9 |
| 引脚 11 | Q0 — Decoded output 0 |
| 引脚 12 | Q1 — Decoded output 1 |
| 引脚 13 | Q2 — Decoded output 2 |
| 引脚 14 | Q3 — Decoded output 3 |
| 引脚 15 | CLK — Clock input |
| 引脚 16 | VDD — Positive supply |
典型应用
CD4017BF 适用于 6 应用s: Ten-Step LED Chaser, Stepper-Motor Step Sequencing, Relay Sequence Controller, Divide-by-Ten Clock Module, Industrial State Selector, Test and Measurement Pulse Counter.
Ten-Step LED Chaser
The CD4017BF fits a ten-step LED chaser because its ten decoded outputs correspond directly to count states 0 through 9. Each output can enable one indicator channel through a suitable driver and current-limiting resistor, producing a repeating visual sequence without a microcontroller. Its 3 V to 18 V supply range supports integration with CD4000 CMOS logic, while the clock input establishes the animation rate. Keep each LED branch electrically isolated from the counter output where required, and use transistor drivers when the total indicator current exceeds the published output capability.
推荐
Stepper-Motor Step Sequencing
The CD4017BF can generate ten decoded sequencing states for a stepper-motor or discrete multi-stage control circuit. The ten outputs select external drive channels in a defined order, while the clock input advances the sequence and the reset input returns it to the starting state. Its 3 V to 18 V operating range makes it appropriate for CMOS control systems, but the motor windings and power devices must be isolated through transistors or other driver stages. Confirm output loading, pulse timing, and reset behavior in the manufacturer datasheet before connecting load hardware.
推荐
Relay Sequence Controller
The CD4017BF is useful in a relay sequence controller because its ten decoded outputs activate one selected stage per count. A clock source can step through the sequence, the clock-inhibit input can pause progression, and reset can restore the initial condition. The 3 V to 18 V supply range allows operation from established CMOS control rails, while the 16-pin PDIP package supports through-hole assembly or socketed prototyping. Use driver transistors or suitable relay interfaces so the decoded outputs are not asked to exceed their specified current capability.
推荐
Divide-by-Ten Clock Module
The CD4017BF can divide an incoming clock into ten decoded states for use as a decade-based timing reference. The first ten clock transitions advance the decoded outputs through their sequence, after which the internal counter rolls over according to the CD4000 design. Its 3 V to 18 V operating range supports integration into legacy CMOS timing circuits. For an accurate time base, provide a stable clock source, observe published propagation-delay limits, and account for output jitter when the decoded signal drives a downstream counter or display stage.
推荐
Industrial State Selector
The CD4017BF works well in an industrial state selector where one of ten machine states must activate at a time. Its decoded outputs reduce the control burden by presenting a direct indication for each count, while reset and clock-inhibit inputs provide basic operating commands. The broad 3 V to 18 V supply range permits use with compatible CMOS control voltages, and the through-hole PDIP-16 package supports maintainable industrial assembly. Use isolation or transistor interfaces for relays, solenoids, and high-energy loads, and validate timing at the lowest intended supply voltage.
推荐
Test and Measurement Pulse Counter
The CD4017BF can count incoming pulses and expose their progress through ten decoded outputs, making it useful for simple bench counters and repetitive-event indicators. The 3 V to 18 V supply range supports laboratory control systems based on CD4000 CMOS logic, and the reset input provides a convenient way to restart each measurement. Clock edges must remain clean and within the manufacturer’s timing limits for reliable counting. Use the decoded outputs to indicate count intervals, and drive external instruments or displays through suitable interface circuits rather than directly loading the counter outputs.
推荐
推荐产品汇总
工程参考数据： CD4017BF ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CD4017BE | HEF4017BP | MC14017BCP |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | NXP | onsemi |
| Package | PDIP-16 | PDIP-16 | DIP-16 | DIP-16 |
| Function | CMOS decade counter with 10 decoded outputs | CMOS decade counter | CD4000-family decade counter | CD4000-family decade counter |
| Logic Family | CD4000 | CD4000 | HEF4000 | 14000 |
| Number of Decoded Outputs | 10 outputs | 10 outputs | 10 outputs | 10 outputs |
| Number of Pins | 16 pins | 16 pins | 16 pins | 16 pins |
| Mounting Style | Through-hole | Through-hole | Through-hole | Through-hole |
关键差异点
- Exact manufacturer family match for an existing CD4017BF footprint （对比 CD4017BE)
- Broader legacy supply compatibility within the qualified CD4000 design （对比 HEF4017BP)
- Established CD4017 decade-counter sequencing behavior （对比 MC14017BCP)
设计说明
Place the supply-bypass capacitor close to the VDD and VSS pins and provide a low-impedance return path to the ground plane or equivalent ground wiring. Because the CD4017BF operates across 3 V to 18 V, the bypass network and board insulation should be suitable for the maximum installed supply. Do not estimate current consumption from the decoded-output state; the operating current depends on supply voltage, switching activity, and the loads attached to the outputs.
Route the clock and clock-inhibit traces away from inductive loads and high-current switching paths to reduce false clock transitions. Keep the reset trace short and avoid routing it adjacent to the clock when pulse-like interference could cause unintended state changes. For a relay or motor design, place transistor or driver circuitry at the board edge and keep high-current loops physically separated from the counter and its timing inputs.
Do not connect LEDs, relays, or motor windings directly unless the decoded output’s published current and duty-cycle limits are satisfied. Use current-limiting resistors for LEDs and suitable transistor or relay-driver stages for inductive loads. Also avoid leaving clock, clock-inhibit, or reset inputs floating; pull them to a defined inactive logic level when the source may be disconnected during power-up, reset, or servicing.
Use a clean clock edge and check propagation delay when the decoded output is used for a time-critical action. Cascaded counters should include reset coordination so that downstream states begin at known values. At the lowest intended supply voltage, verify that the clock amplitude and transition rate satisfy the manufacturer’s input requirements, and allow for the response delay between a clock transition and the corresponding decoded output change.
合规信息
The CD4017BF is a general-purpose CD4000 CMOS logic IC rather than an automotive-qualified device. RoHS, REACH, lead-free, halogen-free, and conflict-minerals declarations require confirmation for the exact manufacturer ordering option.
