DSPIC33FJ128MC706A-H/PT - 16-bit DSC, 128KB Flash, 64-TQFP | Microchip
料号： DSPIC33FJ128MC706A-H/PT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $11.5 | $11.50 |
| 10 | $10.35 | $103.50 |
| 100 | $8.95 | $895.00 |
| 500 | $7.85 | $3,925.00 |
| 1,000 | $6.95 | $6,950.00 |
DSPIC33FJ128MC706A-H/PT 概述
A Digital Signal Controller is a hybrid architecture that combines a microcontroller's deterministic control peripherals with a DSP's multiply-accumulate (MAC) throughput. The dsPIC33F core executes one 16-bit instruction per cycle with hardware single-cycle MAC and barrel shifter, placing it in the device hierarchy: DSC -> DSP/MCU hybrid -> 16-bit MCU family -> embedded controller -> semiconductor. This category targets real-time control loops that need fixed-point math, such as Park/Clarke transforms in motor drives.
Key features of the DSPIC33FJ128MC706A-H/PT include a 6-channel PWM module with complementary outputs and dead-time control suitable for 3-phase inverters, a 10-bit ADC with up to 16 channels and dedicated Sample-and-Hold, on-chip CAN 2.0B peripheral, and a motor-control PWM specifically tuned for field-oriented control (FOC) of brushless DC, AC induction, and switched reluctance motors. The 64-pin TQFP footprint provides ample I/O for power-module gate drivers and analog feedback paths.
The DSP engine uses a modified Harvard architecture with separate program and data buses plus a DSP-specific ALU supporting 17-bit x 17-bit integer multiplication in a single cycle. Hardware loop buffers and zero-overhead DO/REPEAT instructions accelerate inner-loop DSP code such as FIR filters and Park transforms commonly used in FOC firmware. The -H temperature grade extends operation up to +150C junction, making the part appropriate for under-hood automotive and harsh-industrial environments.
Typical applications include brushless DC (BLDC) motor drives, 3-phase AC induction motor control, switched reluctance motor drives, Uninterruptible Power Supply (UPS) inverters, and industrial automation controllers. The integrated CAN peripheral and motor-control PWM simplify field-oriented-control designs by eliminating external DSP co-processors.
When designing with the DSPIC33FJ128MC706A-H/PT, allocate adequate Flash for FOC lookup tables (sine/cosine, inverse Park) and ensure ADC sample timing aligns with the PWM period to minimize sample-to-PWM jitter. The device operates from 3.0 V to 3.6 V; add 100 nF decoupling near each VDD/VSS pair and 10 uF bulk at the regulator output.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives within the dsPIC33FJ family, and practical motor-control design notes that complement the manufacturer datasheet and help engineers select the right DSC variant for their drive topology.
直接替换替代料： DSPIC33FJ128MC706A-H/PT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DSPIC33FJ128MC706A-H/PT （相同外形与封装尺寸） ——差异在于 Package, Core Architecture, CAN, Maximum CPU Speed, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
DSPIC33FJ128MC706A-I/PT
✅ 直接替换✓ 有现货
$5.2 / 个
查看数据手册 →DSPIC33FJ128MC706-H/PT
✅ 直接替换📋 参考替代料（不在目录中）
DSPIC33FJ128MC506A-H/PT
✅ 直接替换✓ 有现货
$3.9 / 个
查看数据手册 →DSPIC33FJ128MC506A-I/PT
✅ 直接替换✓ 有现货
$3.2 / 个
查看数据手册 →DSPIC33FJ128MC506A-E/PT
✅ 直接替换✓ 有现货
$6.9 / 个
查看数据手册 →DSPIC33FJ128MC706A-H/PT 最大额定值与电气特性
| Core Architecture | dsPIC33F (16-bit DSC) |
| Program Memory (Flash) | 128 KB (128K x 8) |
| Maximum CPU Speed | 40 MIPS (20 MHz MIPS-rated) |
| Operating Voltage (VDD) | 3.0 V to 3.6 V |
| 工作温度范围 | -40C to +150C (-H grade) |
| 封装 | 64-pin TQFP (PT) 10x10 mm |
| 安装类型 | Surface Mount |
| ADC | 10-bit, up to 16 channels |
| Motor Control PWM | 6-channel with complementary outputs and dead-time |
| CAN | 1x CAN 2.0B |
| UART | 2x UART |
| SPI | 2x SPI |
| I2C | 1x I2C |
| Timers | 5x 16-bit, 1x 32-bit |
| RoHS 状态 | Compliant |
| Lead-Free | Yes |
DSPIC33FJ128MC706A-H/PT 引脚配置
| 引脚 1 | OSC1/RA0 — Crystal oscillator input / GPIO |
| 引脚 2 | OSC2/RA1 — Crystal oscillator output / GPIO |
| 引脚 3 | RA2 — GPIO |
| 引脚 4 | RA3 — GPIO |
| 引脚 5 | RA4 — GPIO |
| 引脚 6 | RA5 — GPIO |
| 引脚 7 | MCLR — Master Clear (reset) input |
| 引脚 8 | RA7 — GPIO |
| 引脚 9 | VDD — Power supply (3.3V) |
| 引脚 10 | VSS — Ground |
| 引脚 11 | RB0 — GPIO / AN0 |
| 引脚 12 | RB1 — GPIO / AN1 |
| 引脚 13 | RB2 — GPIO / AN2 |
| 引脚 14 | RB3 — GPIO / AN3 |
| 引脚 15 | RB4 — GPIO / AN4 |
| 引脚 16 | RB5 — GPIO / AN5 |
| 引脚 17 | RB6 — GPIO / AN6 / PGEC1 |
| 引脚 18 | RB7 — GPIO / AN7 / PGED1 |
| 引脚 19 | RB8 — GPIO / AN8 |
| 引脚 20 | RB9 — GPIO / AN9 |
| 引脚 21 | RB10 — GPIO / AN10 |
| 引脚 22 | RB11 — GPIO / AN11 |
| 引脚 23 | RB12 — GPIO / AN12 |
| 引脚 24 | RB13 — GPIO / AN13 |
| 引脚 25 | VDD — Power supply (3.3V) |
| 引脚 26 | VSS — Ground |
| 引脚 27 | RC1 — GPIO |
| 引脚 28 | RC2 — GPIO |
| 引脚 29 | RC3 — GPIO |
| 引脚 30 | RC4 — GPIO |
| 引脚 31 | RD0 — GPIO |
| 引脚 32 | RD1 — GPIO |
| 引脚 33 | RD2 — GPIO |
| 引脚 34 | RD3 — GPIO |
| 引脚 35 | RD4 — GPIO |
| 引脚 36 | RD5 — GPIO |
| 引脚 37 | RD6 — GPIO |
| 引脚 38 | RD7 — GPIO |
| 引脚 39 | RD8 — GPIO |
| 引脚 40 | RD9 — GPIO |
| 引脚 41 | VDD — Power supply (3.3V) |
| 引脚 42 | VSS — Ground |
| 引脚 43 | RD11 — GPIO |
| 引脚 44 | RD12 — GPIO |
| 引脚 45 | RD13 — GPIO |
| 引脚 46 | RD14 — GPIO |
| 引脚 47 | RD15 — GPIO |
| 引脚 48 | RF0 — GPIO |
| 引脚 49 | RF1 — GPIO |
| 引脚 50 | RF2 — GPIO |
| 引脚 51 | RF3 — GPIO |
| 引脚 52 | RF4 — GPIO |
| 引脚 53 | PWM3L — PWM 3 Low-side output |
| 引脚 54 | PWM3H — PWM 3 High-side output |
| 引脚 55 | PWM2L — PWM 2 Low-side output |
| 引脚 56 | VDD — Power supply (3.3V) |
| 引脚 57 | VSS — Ground |
| 引脚 58 | PWM2H — PWM 2 High-side output |
| 引脚 59 | PWM1L — PWM 1 Low-side output |
| 引脚 60 | PWM1H — PWM 1 High-side output |
| 引脚 61 | RF5 — GPIO |
| 引脚 62 | RF6 — GPIO |
| 引脚 63 | C1RX/C2RX — ECAN1/ECAN2 Receive |
| 引脚 64 | C1TX/C2TX — ECAN1/ECAN2 Transmit |
典型应用
DSPIC33FJ128MC706A-H/PT 适用于 7 应用s: Brushless DC (BLDC) Motor Drive, Field-Oriented Control (FOC) of PMSM Motors, 3-Phase AC Induction Motor Control, Switched Reluctance Motor (SRM) Drive, Uninterruptible Power Supply (UPS) Inverter, Industrial Servo Drive Controller, Solar Inverter / Microinverter.
Brushless DC (BLDC) Motor Drive
The DSPIC33FJ128MC706A-H/PT is purpose-built for BLDC motor control with its 6-channel complementary PWM and 40 MIPS DSP engine. The integrated PWM module generates three-phase switching signals with programmable dead-time insertion (typically 1-2 us), directly driving half-bridge gate drivers such as the Microchip MCP8021 or IRS2003. At 40 MIPS, the core completes Clarke and Park transforms plus two PI loops within a 50 us PWM period at 20 kHz, leaving margin for commutation interrupts.
推荐
Field-Oriented Control (FOC) of PMSM Motors
Field-oriented control of permanent magnet synchronous motors benefits from the DSPIC33FJ128MC706A-H/PT's single-cycle MAC unit and hardware DO/REPEAT loops. The 128 KB Flash holds full FOC firmware including sine/cosine lookup tables, sensorless observer code, and reference ramp generators. The 16-channel ADC simultaneously samples phase currents via dedicated Sample-and-Hold, synchronized to PWM center-aligned triggers, ensuring deterministic current-loop timing for high-torque low-speed operation.
推荐
3-Phase AC Induction Motor Control
For industrial 3-phase induction motor drives, the DSPIC33FJ128MC706A-H/PT executes V/Hz control or indirect FOC with slip compensation at speeds up to several thousand RPM. The 10-bit ADC with 16 channels monitors stator currents and DC-bus voltage, while the CAN 2.0B peripheral enables networked multi-drive installations communicating with a PLC or industrial gateway. The -H temperature grade supports under-hood and outdoor cabinet installations up to +150C junction.
推荐
Switched Reluctance Motor (SRM) Drive
Switched reluctance motors require independent control of each phase leg and fast current chopping; the DSPIC33FJ128MC706A-H/PT provides six independent PWM channels suitable for the asymmetric half-bridge topology typical of SRM drives. Current hysteresis control runs at up to 60 kHz with the 40 MIPS core computing torque-sharing functions between phases. The 128 KB Flash accommodates SRM-specific commutation tables and demagnetization voltage monitoring algorithms.
推荐
Uninterruptible Power Supply (UPS) Inverter
In UPS inverter applications, the DSPIC33FJ128MC706A-H/PT generates a 50/60 Hz sinusoidal PWM driving an H-bridge or three-phase inverter leg, with closed-loop voltage regulation maintaining output within +/-2% under varying loads. The DSP engine runs the SPWM or SVPWM modulator and RMS voltage calculation within a sub-millisecond control loop. The CAN interface allows status reporting to a system supervisor, while UART links to a front-panel HMI for local monitoring.
推荐
Industrial Servo Drive Controller
In closed-loop servo positioning systems, the DSPIC33FJ128MC706A-H/PT acts as the position/velocity/current controller, communicating encoder feedback via QEI (Quadrature Encoder Interface) and driving a power stage with sinusoidal PWM. The hardware QEI module counts quadrature pulses without CPU intervention, while the DSP engine computes the trajectory profiler and PID controllers. CANopen or proprietary CAN protocols enable integration into multi-axis motion networks using the on-chip CAN peripheral.
推荐
Solar Inverter / Microinverter
In solar microinverter topologies the DSPIC33FJ128MC706A-H/PT performs MPPT (Maximum Power Point Perturb-and-Observe) and grid-tie inverter control, generating 50/60 Hz synchronized sinusoidal output current. The DSP MAC executes the MPPT algorithm in microseconds while the ADC samples PV panel voltage and current. Anti-islanding protection algorithms fit within the 128 KB Flash budget, and the CAN interface supports daisy-chained multi-panel monitoring systems on commercial rooftops.
推荐
推荐产品汇总
工程参考数据： DSPIC33FJ128MC706A-H/PT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DSPIC33FJ128MC706A-I/PT | DSPIC33FJ128MC706-H/PT | DSPIC33FJ128MC506A-H/PT | DSPIC33FJ128MC506A-I/PT | DSPIC33FJ128MC506A-E/PT |
|---|---|---|---|---|---|---|
| Package | 64-pin TQFP (PT) 10x10 mm | 64-pin TQFP (PT) - same | 64-pin TQFP (PT) - same | 64-pin TQFP (PT) - same | 64-pin TQFP (PT) - same | 64-pin TQFP (PT) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128 KB | 128 KB (same) | 128 KB (same) | 64 KB (-50%) | 64 KB (-50%) | 64 KB (-50%) |
| CPU Speed | 40 MIPS | 40 MIPS (same) | 40 MIPS (same) | 40 MIPS (same) | 40 MIPS (same) | 40 MIPS (same) |
| Operating Temperature | -40C to +150C (-H) | -40C to +85C (-I) | -40C to +150C (-H) | -40C to +150C (-H) | -40C to +85C (-I) | -40C to +125C (-E) |
| Silicon Revision | A | A | Pre-A (original) | A | A | A |
| Core | dsPIC33F (16-bit DSC) | dsPIC33F (same) | dsPIC33F (same) | dsPIC33F (same) | dsPIC33F (same) | dsPIC33F (same) |
关键差异点
- Maximum Flash density in the 64-pin TQFP dsPIC33FJ family （对比 DSPIC33FJ128MC506A-H/PT)
- Highest junction temperature grade available (-H = +150C) （对比 DSPIC33FJ128MC706A-I/PT)
- Silicon revision A with errata fixes over original revision （对比 DSPIC33FJ128MC706-H/PT)
- dsPIC33F DSC architecture with single-cycle MAC for FOC （对比 PIC24FJ128GB606-I/PT)
设计说明
The DSPIC33FJ128MC706A-H/PT operates from a single 3.0 V to 3.6 V supply and draws approximately 60 mA at 40 MIPS with all peripherals active. Use a low-noise LDO such as the MCP1754S-330E with a 10 uF ceramic output capacitor to provide a clean 3.3 V rail. Place a 100 nF decoupling capacitor within 5 mm of every VDD/VSS pair (the part has four pairs at pins 9/10, 25/26, 41/42, and 56/57) and add a 10 uF bulk at the regulator output to suppress switching noise from adjacent gate drivers.
Estimated: with theta_JA of approximately 45 C/W for the 64-pin TQFP-10x10, the junction temperature rise at 60 mA and 3.3 V (0.2 W dissipation) is about 9 C above ambient. Add a copper thermal land pattern under the exposed thermal pad to reduce theta_JA by 30-40% in high-ambient-temperature motor-drive enclosures. Place the 64-pin TQFP at least 10 mm from the switching power stage to minimize conducted EMI coupling on analog inputs.
The 10-bit ADC has a 500 ksps throughput and is sensitive to switching-noise coupling. Use star-ground topology with the ADC ground reference tied directly to the GND pin closest to the analog inputs (VSS at pin 26 or 42). Route ADC traces away from PWM switching signals and add a 100 ohm series resistor with 1 nF capacitor RC filter on each analog input for noise rejection above 1.6 MHz, well above the 50 us PWM period.
Do not exceed 3.6 V on any I/O pin even though some dsPIC33F variants advertise 5 V tolerance - this specific part has 3.3 V-only I/O. Configure the JTAG/debugger PGEC1/PGED1 pins (RB6/RB7) only as ICD debug pins to avoid contention with PGEC1 peripheral remapping. When using CAN, add a 120 ohm termination resistor at each end of the bus and avoid stubs longer than 100 mm to prevent reflections per ISO 11898.
When porting code from dsPIC33FJ128MC706 to the 'A' revision, check the silicon errata for changes to ADC calibration, PWM duty-cycle resolution, and I2C slave address handling. The 'A' revision generally adds fixes but may have minor register-access changes that require recompilation against the latest MPLAB XC16 DSP library headers.
合规信息
RoHS compliant per Microchip product page. -H temperature grade supports +150C junction but is NOT AEC-Q100 qualified - for automotive applications use AEC-Q100-qualified parts from the dsPIC33 automotive family. Conflict-minerals compliance per Microchip standard policy.
